AN2329 Freescale Semiconductor / Motorola, AN2329 Datasheet - Page 19

• Manufacturer Part Number: AN2329
• Description: Interfacing the MSC8101 to SDRAM on the MSC8101ADS
• Manufacturer: Freescale Semiconductor / Motorola

PSDMR
TYPE
RESET
TYPE
RESET
Name
RFEN
2–4
PBI
OP
RFRC
0
1
Bit 0
PBI
16
0
0
PSDMR configures operations pertaining to the SDRAM machine on the system bus. All possible bit
settings are shown, and, for each bit, the selected setting for this application is highlighted in bold.
RFEN
17
1
0
0
Reset
PRETOACT
0
0
0
Freescale Semiconductor, Inc.
18
2
0
0
60x SDRAM Mode Register
For More Information On This Product,
Page-Based Interleaving
Selects the address multiplexing method. PBI
works in conjunction with PSDMR[SDA10].
Refresh Enable
Indicates that the SDRAM needs refresh
services.
SDRAM Operation
Determines which operation occurs when the
SDRAM device is accessed. If Multi-Master
Bus mode is in effect on the system bus or
the SDRAM port size is 8-/16-bit or the
SDRAM is connected to the BADDR lines
(not needed for 64-/32-bit port size), the bus
master must supply the mode register data
on the low bits of the address during the
access.
NOTE: The selection of OP depends on the
operation during SDRAM initialization.
OP
19
3
0
0
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20
4
0
0
ACTTORW
Description
21
Table 22. PSDMR Settings
5
0
0
SDAM
22
6
0
0
23
BL
7
0
0
R/W
R/W
LDOTOPRE
24
8
Programming the MSC8101 SDRAM Machine
0
0
BSMA
0
1
0
1
000
001
010
011
100
101
110
111
25
9
0
0
Bank-based interleaving.
Page-based interleaving (normal
operation).
Refresh services are not required.
Refresh services are required.
Normal operation.
CBR refresh, used in SDRAM initialization.
Self refresh (for debug purpose).
Mode Register write, used in SDRAM
initialization.
Precharge bank (for debug purpose).
Precharge all banks, used in SDRAM
initialization.
Activate bank (for debug purpose).
Read/write (for debug purpose).
10
26
0
0
WRC
11
27
0
0
Settings
EAMUX BUFCMD
SDA10
12
28
0
0
0x10190
13
29
0
0
14
30
0
0
RFRC
CL
15
31
0
0
19