AN2329 Freescale Semiconductor / Motorola, AN2329 Datasheet - Page 22

• Manufacturer Part Number: AN2329
• Description: Interfacing the MSC8101 to SDRAM on the MSC8101ADS
• Manufacturer: Freescale Semiconductor / Motorola

Programming the MSC8101 SDRAM Machine
PSRT
22
RESET
TYPE
Name
PSRT
BUFCMD
0–7
Name
30–31
CL
29
Bit 0
PSRT determines the timer period for SDRAM refresh requests.
Reset
0
60x Bus-Assigned SDRAM Refresh Timer
0
Reset
0
0
Refresh Timer Period
Determines the timer period according to the following equation:
This timer generates refresh requests for all valid banks that selected a SDRAM machine assigned to the
system bus and is refresh-enabled (PSDMR[RFEN] = 1). Each time the timer expires, all banks that
qualify generate a bank staggering auto refresh request using the SDRAM machine.
Example: For a 25 MHz system bus clock and a required service rate of 15.6 µs, given
MPTPR[PTP] = 32, the PSRT value should be 12 decimal. 12/(25 MHz/32) = 15.36 µs, which is less than
the required service period of 15.6 µs.
TimerPeriod = (PSRT + 1) x
Freescale Semiconductor, Inc.
Command Buffer
If external buffers are placed on the control
lines going to both the SDRAM and address
lines, setting the BUFCMD bit causes all
SDRAM control lines except CS to be
asserted for two cycles, instead of one. In
multi-master bus mode, external buffers can
be placed on the command strobes, except
CS, as well as on the address lines. If the
additional delay of the buffers endangers the
device setup time, BUFCMD should be set,
which causes the memory controller to add a
cycle for each SDRAM command.
CAS Latency
Defines the timing for first read data after
SDRAM samples a column address.
1
0
For More Information On This Product,
Table 22. PSDMR Settings (Continued)
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Table 23. PSRT Bit Descriptions
Description
2
0
3
MPTPR[PTP] + 1
0
Bus frequency
PSRT
R/W
Description
4
0
0
1
00
01
10
11
Normal timing for the control lines.
All control lines except CS are asserted for
two cycles.
Reserved
1.
2.
3.
5
0
Settings
6
0
0x1019C
7
0