AN2329 Freescale Semiconductor / Motorola, AN2329 Datasheet - Page 24

• Manufacturer Part Number: AN2329
• Description: Interfacing the MSC8101 to SDRAM on the MSC8101ADS
• Manufacturer: Freescale Semiconductor / Motorola

Programming the MSC8101 SDRAM Machine
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writemmr32 PSDMR 0xc2689212
writemem32 0x20000020 0x0
writemmr32 PSDMR 0xaa689212
writemem32 0x20000020 0x0
writemmr32 PSDMR 0x8a689212
writemem32 0x20000000 0x0
writemem32 0x20000000 0x0
writemem32 0x20000000 0x0
writemem32 0x20000000 0x0
writemem32 0x20000000 0x0
writemem32 0x20000000 0x0
writemem32 0x20000000 0x0
writemem32 0x20000000 0x0
writemmr32 PSDMR 0x9A689212
writemem32 0x20000032 0x0
writemmr32 OR2 0xFF0030A0
writemmr32 BR2 0x20000041
writemmr32 PSDMR 0xc2689212
writemmr8 PSRT 0x13
writemmr16 MPTPR 0x2800
writemmr8 PSRT 0xe
writemmr32 OR2 0xff803280
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 25. Program SDRAM For the 64-Bit Port Size (Continued)
Command
Command
Table 26. Program SDRAM For the 32-Bit Port Size
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4. Program PSDMR for normal operation.
• SDRAM address multiplex size (SDAM) = 010
• Bank select Multiplexed Address line (BSMA) = 011
• SDRAM A10 control (SDA10) is A8
• Refresh recovery (RFRC) is 3 clock cycles
• Precharge to Activate interval (PRETOACT) = 1 clock cycle
• Activate to read/write interval (ACTTORW) = 1 clock cycle
• Burst length is 4 data beats
• Last data out to Precharge (LDOTOPRE) = 0 cycles
• Write recovery time is 2 cycles
• External Address Multiplexing Enable/Disable (EAMUX) = 0
• Command buffer (BUFCM) is normal (1 clock cycle for all
• CAS latency (CL) = 2
5. Write to a random location in memory.
6. Program the PSDMR register to PRECHARGE all banks.
7. Program the PSDMR register to issue 8 auto refreshes.
8. Write 0x0 to a random location in memory eight times.
9. Program PSDRAM to program the mode register.
0x20000032 indicates a CAS latency of 3-beat and 4-beat bursts.
10. Program the BR2, OR2, and PSDMR2 for normal operation.
• Base address 0x20000000
• Data pipelining is not enabled
• No error correction
• SDRAM Machine is the memory controller of choice
• Bank is valid
11. Program the PSRT.
12. Program the MPTPR.
1. Program the PSRT.
2. Program OR2 for 8 MB.
• Bank size = 16 MB
• There are 11 row address lines and the first row address line
• 4 banks per device
• Bank interleaving is enabled
memory control signals
starts at A8
Explanation
Explanation