FDC37B77X SMSC Corporation, FDC37B77X Datasheet - Page 172
FDC37B77X
Manufacturer Part Number
FDC37B77X
Description
ENHANCED SUPER I/O CONTROLLER WITH WAKE UP FEATURES
Manufacturer
SMSC Corporation
Datasheet
1.FDC37B77X.pdf
(196 pages)
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Note 1: The RESET width is dependent upon the processor clock. The RESET must be active while
CLOCKI
RESET_DRV
NAME
NAME
t1
t2
t1
t2
t4
the clock is running and stable.
Clock Cycle Time for 14.318MHZ
Clock High Time/Low Time for 14.318MHz
Clock Cycle Time for 32KHZ
Clock High Time/Low Time for 32KHz
Clock Rise Time/Fall Time (not shown)
RESET width (Note 1)
DESCRIPTION
DESCRIPTION
FIGURE 7A - INPUT CLOCK TIMING
FIGURE 7B - RESET TIMING
t1
172
t4
t2
MIN
MIN
1.5
31.25
16.53
TYP
t2
TYP
70
35
MAX
MAX
5
UNITS
UNITS
ns
ns
ns
s
s
s
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