FDC37C672QFP SMSC Corporation, FDC37C672QFP Datasheet - Page 23

• Manufacturer Part Number: FDC37C672QFP
• Description: ENHANCED SUPER I/O CONTROLLER WITH FAST IR
• Manufacturer: SMSC Corporation

Enhanced Super I/O Controller with Fast IR
Datasheet
6.1.3
SMSC FDC37C672
Digital Output Register (DOR)
Address 3F2 READ/WRITE
The DOR controls the drive select and motor enables of the disk interface outputs. It also contains the
enable for the DMA logic and a software reset bit. The contents of the DOR are unaffected by a software
reset. The DOR can be written to at any time.
BIT 0 and 1 DRIVE SELECT
These two bits are binary encoded for the four drive selects DS0 -DS3, thereby allowing only one drive to
be selected at one time.
BIT 2 nRESET
A logic "0" written to this bit resets the Floppy disk controller. This reset will remain active until a logic "1"
is written to this bit. This software reset does not affect the DSR and CCR registers, nor does it affect the
other bits of the DOR register. The minimum reset duration required is 100ns, therefore toggling this bit by
consecutive writes to this register is a valid method of issuing a software reset.
BIT 3 DMAEN
PC/AT and Model 30 Mode:
Writing this bit to logic "1" will enable the DRQ, nDACK, TC and FINTR outputs. This bit being a logic "0"
will disable the nDACK and TC inputs, and hold the DRQ and FINTR outputs in a high impedance state.
This bit is a logic "0" after a reset and in these modes.
PS/2 Mode:
In this mode the DRQ, nDACK, TC and FINTR pins are always enabled. During a reset, the DRQ,
nDACK, TC, and FINTR pins will remain enabled, but this bit will be cleared to a logic "0".
BIT 4 MOTOR ENABLE 0
This bit controls the MTR0 disk interface output. A logic "1" in this bit will cause the output pin to go active.
BIT 5 MOTOR ENABLE 1
This bit controls the MTR1 disk interface output. A logic "1" in this bit will cause the output pin to go active.
BIT 6 MOTOR ENABLE 2
This bit controls the MTR2 disk interface output. A logic "1" in this bit will cause the output pin to go active.
RESET
COND.
PRELIMINARY DATASHEET
MOT
EN3
7
0
MOT
EN2
6
0
MOT
EN1
5
0
Page 23
MOT
EN0
4
0
DMAEN nRESE
3
0
T
2
0
DRIVE
SEL1
1
0
DRIVE
SEL0
0
0
Rev. 10-29-03