LM3S1512 Luminary Micro, Inc, LM3S1512 Datasheet - Page 16
LM3S1512
Manufacturer Part Number
LM3S1512
Description
Lm3s1512 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S1512.pdf
(508 pages)
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Table of Contents
Synchronous Serial Interface (SSI) ............................................................................................ 339
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Inter-Integrated Circuit (I
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Analog Comparators ................................................................................................................... 411
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
16
SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 351
SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 353
SSI Data (SSIDR), offset 0x008 ...................................................................................... 355
SSI Status (SSISR), offset 0x00C ................................................................................... 356
SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 358
SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 359
SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 361
SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 362
SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 363
SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 364
SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 365
SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 366
SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 367
SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 368
SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 369
SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 370
SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 371
SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 372
SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 373
SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 374
SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 375
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00 .................................... 417
Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04 ......................................... 418
Analog Comparator Interrupt Enable (ACINTEN), offset 0x08 ........................................... 419
Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10 ......................... 420
Analog Comparator Status 0 (ACSTAT0), offset 0x20 ....................................................... 421
Analog Comparator Status 1 (ACSTAT1), offset 0x40 ....................................................... 421
Analog Comparator Status 2 (ACSTAT2), offset 0x60 ....................................................... 421
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 390
C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 391
C Master Data (I2CMDR), offset 0x008 ......................................................................... 395
C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 396
C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 397
C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 398
C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 399
C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 400
C Master Configuration (I2CMCR), offset 0x020 ............................................................ 401
C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ 403
C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... 404
C Slave Data (I2CSDR), offset 0x008 ........................................................................... 406
C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... 407
C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... 408
C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. 409
C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ 410
2
C) Interface ........................................................................................ 376
Preliminary
July 25, 2008
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