LM3S1911 Luminary Micro, Inc, LM3S1911 Datasheet - Page 244
LM3S1911
Manufacturer Part Number
LM3S1911
Description
Lm3s1911 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S1911.pdf
(450 pages)
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Reset
Reset
Type
Type
Watchdog Timer
Watchdog Raw Interrupt Status (WDTRIS)
Base 0x4000.0000
Offset 0x010
Type RO, reset 0x0000.0000
244
Bit/Field
31:1
0
RO
RO
31
15
0
0
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010
This register is the raw interrupt status register. Watchdog interrupt events can be monitored via
this register if the controller interrupt is masked.
RO
RO
30
14
0
0
reserved
WDTRIS
RO
RO
29
13
0
0
Name
RO
RO
28
12
0
0
RO
RO
27
11
0
0
Type
RO
RO
RO
RO
26
10
0
0
Reset
0x00
RO
RO
25
0
9
0
0
Preliminary
reserved
RO
RO
24
0
8
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Watchdog Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of WDTINTR.
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
RO
RO
19
0
3
0
RO
RO
18
0
2
0
July 26, 2008
RO
RO
17
0
1
0
WDTRIS
RO
RO
16
0
0
0
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