LM3S2730 Luminary Micro, Inc, LM3S2730 Datasheet - Page 95
LM3S2730
Manufacturer Part Number
LM3S2730
Description
Lm3s2730 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S2730.pdf
(423 pages)
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July 25, 2008
Bit/Field
15:5
3:1
17
16
4
0
reserved
reserved
TIMER1
TIMER0
UART0
Name
SSI0
Type
R/W
R/W
R/W
R/W
RO
RO
Reset
0
0
0
0
0
0
Preliminary
Description
Timer 1 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 1.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
Timer 0 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 0.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI0 Clock Gating Control
This bit controls the clock gating for SSI module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART0 Clock Gating Control
This bit controls the clock gating for UART module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
LM3S2730 Microcontroller
95
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