LM3S5652 Luminary Micro, Inc, LM3S5652 Datasheet - Page 180
LM3S5652
Manufacturer Part Number
LM3S5652
Description
Lm3s5652 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S5652.pdf
(703 pages)
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Micro Direct Memory Access (μDMA)
9
180
Micro Direct Memory Access (μDMA)
The LM3S5652 microcontroller includes a Direct Memory Access (DMA) controller, known as
micro-DMA (μDMA). The μDMA controller provides a way to offload data transfer tasks from the
Cortex-M3 processor, allowing for more effecient use of the processor and the expanded available
bus bandwidth. The μDMA controller can perform transfers between memory and peripherals. It
has dedicated channels for each supported peripheral and can be programmed to automatically
perform transfers between peripherals and memory as the peripheral is ready to transfer more data.
The μDMA controller also supports sophisticated transfer modes such as ping-pong and
scatter-gather, which allows the processor to set up a list of transfer tasks for the controller.
The μDMA controller has the following features:
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ARM PrimeCell® 32-channel configurable µDMA controller
Support for multiple transfer modes:
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Dedicated channels for supported peripherals
One channel each for receive and transmit path for bidirectional peripherals
Dedicated channel for software-initiated transfers
Independently configured and operated channels
Per-channel configurable bus arbitration scheme
Two levels of priority
Design optimizations for improved bus access performance between µDMA controller and the
processor core:
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Data sizes of 8, 16, and 32 bits
Source and destination address increment size of byte, half-word, word, or no increment
Maskable device requests
Optional software initiated requests for any channel
Interrupt on transfer completion, with a separate interrupt per channel
Basic, for simple transfer scenarios
Ping-pong, for continuous data flow to/from peripherals
Scatter-gather, from a programmable list of arbitrary transfers initiated from a single request
µDMA controller access is subordinate to core access
RAM striping
Peripheral bus segmentation
Preliminary
June 02, 2008
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