LM3S5652 Luminary Micro, Inc, LM3S5652 Datasheet - Page 328
LM3S5652
Manufacturer Part Number
LM3S5652
Description
Lm3s5652 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S5652.pdf
(703 pages)
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Reset
Reset
Type
Type
Watchdog Timer
Watchdog Masked Interrupt Status (WDTMIS)
Base 0x4000.0000
Offset 0x014
Type RO, reset 0x0000.0000
328
Bit/Field
31:1
RO
RO
0
31
15
0
0
RO
RO
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014
This register is the masked interrupt status register. The value of this register is the logical AND of
the raw interrupt bit and the Watchdog interrupt enable bit.
30
14
0
0
RO
RO
29
13
WDTMIS
reserved
0
0
Name
RO
RO
28
12
0
0
RO
RO
27
11
0
0
Type
RO
RO
RO
RO
26
10
0
0
RO
RO
Reset
25
0x00
0
9
0
0
reserved
Preliminary
RO
RO
24
0
8
0
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Watchdog Masked Interrupt Status
Gives the masked interrupt state (after masking) of the WDTINTR
interrupt.
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
RO
RO
19
0
3
0
RO
RO
18
0
2
0
RO
RO
17
0
1
0
June 02, 2008
WDTMIS
RO
RO
16
0
0
0
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