LM3S5652 Luminary Micro, Inc, LM3S5652 Datasheet - Page 425
LM3S5652
Manufacturer Part Number
LM3S5652
Description
Lm3s5652 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S5652.pdf
(703 pages)
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15.2.4.6 Freescale SPI Frame Format with SPO=1 and SPH=1
15.2.4.7 MICROWIRE Frame Format
June 02, 2008
The transfer signal sequence for Freescale SPI format with SPO=1 and SPH=1 is shown in Figure
15-9 on page 425, which covers both single and continuous transfers.
Figure 15-9. Freescale SPI Frame Format with SPO=1 and SPH=1
SSIClk
SSIFss
Note:
In this configuration, during idle periods:
■
■
■
■
■
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low. The master SSITx output pad is enabled.
After a further one-half SSIClk period, both master and slave data are enabled onto their respective
transmission lines. At the same time, SSIClk is enabled with a falling edge transition. Data is then
captured on the rising edges and propagated on the falling edges of the SSIClk signal.
After all bits have been transferred, in the case of a single word transmission, the SSIFss line is
returned to its idle high state one SSIClk period after the last bit has been captured.
For continuous back-to-back transmissions, the SSIFss pin remains in its active Low state, until
the final bit of the last word has been captured, and then returns to its idle state as described above.
For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words
and termination is the same as that of the single word transfer.
Figure 15-10 on page 426 shows the MICROWIRE frame format, again for a single frame. Figure
15-11 on page 427 shows the same format when back-to-back frames are transmitted.
SSIRx
SSITx
SSIClk is forced High
SSIFss is forced High
The transmit data line SSITx is arbitrarily forced Low
When the SSI is configured as a master, it enables the SSIClk pad
When the SSI is configured as a slave, it disables the SSIClk pad
Q is undefined.
Q
MSB
MSB
Preliminary
4 to 16 bits
LSB
LSB
LM3S5652 Microcontroller
Q
425
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