LM3S5652 Luminary Micro, Inc, LM3S5652 Datasheet - Page 533
LM3S5652
Manufacturer Part Number
LM3S5652
Description
Lm3s5652 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S5652.pdf
(703 pages)
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18
18.1
June 02, 2008
Univeral Serial Bus (USB) Controller
The Stellaris
in point-to-point communications with USB host, device, or OTG functions. The controller complies
with the USB 2.0 standard, which includes suspend and resume signaling. Three configurable
endpoints (1-3) with a dynamic sizable FIFO support multiple packet queueing. DMA access to the
FIFO allows minimal interference from system software. Software-controlled connect and disconnect
allows flexibility during USB device start-up. The controller complies with OTG standard's session
request protocol (SRP) and host negotiation protocol (HNP).
The Stellaris
■
■
■
■
■
■
■
■
Block Diagram
Figure 18-1. USB Module Block Diagram
Standards-based
USB 2.0 full-speed (12 Mbps) and low-speed (1.5 Mbps) operation
USB On-The-Go (OTG) mode
Integrated PHY
4 transfer types: control, interrupt, bulk, and isochronous
1 dedicated bi-directional control endpoint
3 receive and 3 transmit configurable endpoints
4 KB dedicated endpoint memory
–
–
USB Data Lines
Direct Memory Access
One endpoint may be defined for double-buffered 1023-byte isochronous packet size
D+ and D-
®
®
USB controller operates as a function controller for a full-speed or low-speed device
USB module has the following features:
USB PHY
USB FS/LS
PHY
Synchronization
Data Sync
HNP/SRP
Timers
UTM
Preliminary
Encode/Decode
CRC Gen/Check
Packet Decode
Packet Encode
Endpoints
Combine
EP0 – 3
Control
Packet
Endpoint Control
Transaction
Buff
Buff
Scheduler
Rx
Cycle Control
Tx
Transmit
Receive
FIFO RAM
Controller
Host
Buff
Buff
Rx
Tx
LM3S5652 Microcontroller
CPU Interface
Common
EP Reg.
Decoder
Interrupt
Decoder
Regs
Control
Control
Cycle
FIFO
533
DMA
Requests
Interrupts
AHB bus –
Slave mode
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