MT16HTF12864AY-53EC2 Micron, MT16HTF12864AY-53EC2 Datasheet - Page 28

• Manufacturer Part Number: MT16HTF12864AY-53EC2
• Description: DRAM Chip, 512MB, 1GB, 2GB (x64, DR) PC2-3200, PC2-4200, 240-Pin DDR2 SDRAM UDIMM
• Manufacturer: Micron

Notes
pdf: 09005aef80f09084, source: 09005aef80f09068
HTF16C64_128_256x64AG.fm - Rev. B 8/04 EN
1. All voltages referenced to V
2. Tests for AC timing,
3. Outputs measured with equivalent load:
4. AC timing and
5. The AC and DC input level specifications are as
6. Command/Address minimum input slew rate is at
7. Data minimum input slew rate is at 1.0V/ns. Data
characteristics may be conducted at nominal ref-
erence/supply voltage levels, but the related spec-
ifications and device operation are guaranteed for
the full voltage range specified.
of up to 1.0V in the test environment and parame-
ter specifications are guaranteed for the specified
AC input levels under normal use conditions. The
minimum slew rate for the input signals used to
test the device is 1.0V/ns for signals in the range
between V
than 1.0V/ns require the timing parameters to be
derated as specified.
defined in the SSTL_18 standard (i.e., the receiver
will effectively switch as a result of the signal
crossing the AC input level and will remain in that
state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).
1.0V/ns. Command/Address input timing must be
derated if the slew rate is not 1.0V/ns. This is eas-
ily accommodated using
Hold Time Derating Values table.
is referenced from V
V
erenced from V
V
lists the
rate; these are the “base” values.
input timing must be derated if the slew rate is not
1.0V/ns. This is easily accommodated if the tim-
ing is referenced from the logic trip points.
timing (
ing signal and V
ing (
signal and V
table lists the
slew rate. If the DQS/DQS# differential strobe fea-
ture is not enabled, timing is no longer referenced
to the crosspoint of DQS/DQS#. Data timing is
now referenced to V
IL
IL
(
(
AC
DC
t
IH
) for a falling signal.
) for a falling signal. The timing table also
b
t
DS
) is referenced from V
t
IS
IL
Output
(V
b
b
) is referenced from V
IL
OUT
(AC) and V
and
(
t
I
DS
DC
DD
V
)
IL
TT =
IH
) for a falling signal. The timing
b
tests may use a V
(AC) for a falling signal.
t
IH
(
and
V
AC
I
IH
DD
DD
REF
25Ω
b
) for a rising signal and
Q/2
, and electrical AC and DC
(
values for a 1.0V/ns slew
t
AC
, provided the DQS slew
DH
Reference
Point
IH
t
) for a rising signal and
IS
t
SS
PC2-3200, PC2-4200, 240-Pin DDR2 SDRAM UDIMM
IH timing (
b
(AC). Slew rates less
b
.
values for a 1.0V/ns
and the Setup and
IH
(DC) for a rising
IH
t
IL
IS timing (
-to-V
(AC) for a ris-
t
IH
IH
b
t
IH tim-
) is ref-
swing
t
IS
t
DS
b
)
28
10.
11. The intent of the Don’t Care state after completion
12. This is not a device limit. The device will operate
13. It is recommended that DQS be valid (HIGH or
14. The refresh period is 64ms. This equates to an
15. Each byte lane has a corresponding DQS.
16. CK and CK# input slew rate must be ≥ 1V/ns (≥ 2
17. The data valid window is derived by achieving
18.
19. MIN(
8.
9. This maximum value is derived from the refer-
rate is not less than 1.0V/ns. If the DQS slew rate is
less than 1.0V/ns, then data timing is now refer-
enced to V
falling DQS.
t
time windows as valid data transitions. These
parameters are not referenced to a specific voltage
level, but specify when the device output is no
longer driving (
enced test load.
t
t
t
of the postamble is the DQS-driven signal should
either be high, low or High-Z and that any signal
transition within the input switching region must
follow valid input requirements. That is if DQS
transitions high (above V
not transition low (below V
t
with a negative value, but system performance
could be degraded due to bus turnaround.
LOW) on or before the WRITE command. The
case shown (DQS going from High-Z to logic
LOW) applies when no WRITEs were previously in
progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this time,
depending on
average refresh rate of 7.8125µs. However, a
REFRESH command must be asserted at least
once every 70.3µs or
rows of all banks are properly refreshed, 8192
REFRESH commands must be issued every 64ms.
V/ns if measured differentially).
other specifications -
t
derates in direct proportion to the clock duty
cycle and a practical data valid window can be
derived.
t
clock low time and the actual clock high time as
provided to the device (i.e. This value can be
greater than the minimum specification limits for
HZ and
DQSCK (MAX) +
LZ (MIN) will prevail over a
RPRE (MAX) condition.
DQSH(min).
QH (
JIT specification is currently TBD.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MB, 1GB, 2GB (x64, DR)
t
t
CL,
QH =
t
LZ transitions occur in the same access
t
IH
CH) refers to the smaller of the actual
(
t
HP -
AC
t
DQSS.
t
) for a rising DQS and V
HZ) or begins driving (
t
RPST (MAX) condition.
t
t
QHS). The data valid window
HZ (MAX) will prevail over
t
RFC (MAX). To ensure all
t
HP . (
©2004 Micron Technology, Inc. All rights reserved.
IH
DC(min) then it must
t
CK/2),
t
IH
DQSCK (MIN) +
(DC) prior to
t
DQSQ, and
t
IL
LZ).
(
DC
) for a