MT16HTF12864AY-53EC2 Micron, MT16HTF12864AY-53EC2 Datasheet - Page 29

• Manufacturer Part Number: MT16HTF12864AY-53EC2
• Description: DRAM Chip, 512MB, 1GB, 2GB (x64, DR) PC2-3200, PC2-4200, 240-Pin DDR2 SDRAM UDIMM
• Manufacturer: Micron

pdf: 09005aef80f09084, source: 09005aef80f09068
HTF16C64_128_256x64AG.fm - Rev. B 8/04 EN
20.
21. READs and WRITEs with auto precharge are
22. V
23.
24. The minimum READ to internal PRECHARGE
25. Operating frequency is only allowed to change
26. ODT turn-on time
t
percent of the period, less the half period jitter
[
period jitter due to cross talk [
the clock traces.
t
minimum actually applied to the device CK and
CK# inputs.
allowed to be issued before
since
SDRAM devices.
the 256Mb, 512Mb, or 1Gb DDR2 SDRAM data
sheet for more detail.
t
above, if not already an integer, round to the next
highest integer.
period; nWR refers to the
the MR[11,10,9]. Example: For -53E at
ns with
+ (15 ns/3.75 ns) clocks = 4 +(4) clocks = 8 clocks.
time. This parameter is only applicable when
t
tion AL + BL/2 applies. Notwithstanding,
(MIN) has to be satisfied as well. The DDR2
SDRAM device will automatically delay the inter-
nal PRECHARGE command until
been satisfied.
during self refresh mode, precharge power-down
mode, and system reset condition.
leaves high impedance and ODT resistance
begins to turn on. ODT turn-on time
is when the ODT resistance is fully on. Both are
measured from
CL and
HP (MIN) is the lesser of
DAL = (nWR) + (
RTP/(2*
t
JIT(HP)] of the clock source, and less the half
IL
/V
IH
t
RAS lockout feature is supported in DDR2
t
WR programmed to four clocks.
t
t
DDR2 overshoot/undershoot. R
CK) > 1. If
CH). For example,
t
t
AOND.
CK refers to the application clock
t
RP/
t
AON (MIN) is when the device
t
RTP/(2*
t
CK): For each of the terms
t
WR parameter stored in
t
PC2-3200, PC2-4200, 240-Pin DDR2 SDRAM UDIMM
CL minimum and
t
RAS (MIN) is satisfied
t
t
CL and
CK) ≤ 1, then equa-
t
JIT(cross talk)] into
t
RAS (MIN) has
t
t
CH are = 50
AON (MAX)
t
CK = 3.75
t
EFER TO
DAL = 4
t
RAS
t
CH
29
27. ODT turn-off time
28. This parameter has a two clock minimum require-
29.
30.
31. No more than 4 bank ACTIVE commands may be
32.
33. Value is minimum pulse width, not the number of
34. Applicable to Read cycles only. Write cycles gener-
35.
36. This parameter is not referenced to a specific volt-
starts to turn off ODT resistance. ODT turn off
time
impedance. Both are measured from
ment at any
t
CKE registration LOW is guaranteed prior to CK,
CK# being removed in a system RESET condition.
t
during self refresh exit.
issued in a given
restriction still applies. The
applies to all 8 bank DDR2 devices, regardless of
the number of banks already open or closed.
t
command is issued, regardless of the number of
banks already open or closed. If a single-bank
PRECHARGE command is issued,
applies.
devices.
clock registrations.
ally require additional time due to Write recovery
time (
t
tered on three consecutive positive clock edges.
CKE must remain at the valid input level the entire
time it takes to achieve the 3 clocks of registration.
Thus, after any CKE transition, CKE may not tran-
sition from its valid level during the time period of
t
age level, but specified whwen the device output
is no longer driving (
(
DELAY is calculated from
ISXR is equal to
RPA timing applies when the PRECHARGE(ALL)
CKE (MIN) of 3 clocks means CKE must be regis-
IS + 2 *
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
RPRE).
512MB, 1GB, 2GB (x64, DR)
t
t
WR) during auto precharge.
AOF (MAX) is when the bus is in high
t
CK +
t
RPA(MIN) applies to all 8-bank DDR2
t
CK.
t
IH.
t
IS and is used for CKE setup time
t
t
AOF (MIN) is when the device
FAW(min) period.
t
RPST) or beginning to drive
©2004 Micron Technology, Inc. All rights reserved.
t
IS +
t
FAW(min) parameter
t
CK +
t
AOFD.
t
t
RP timing
t
IH so that
RRD(min)