CLA70000 Zarlink Semiconductor, CLA70000 Datasheet - Page 3

• Manufacturer Part Number: CLA70000
• Description: High Density CMOS Gate Arrays
• Manufacturer: Zarlink Semiconductor

Power Supply Distribution
•
•
•
arrays (fig.3) has the flexibility to meet varying applications
needs. Three separate power rings are used, one each for the
internal core logic, intermediate buffer cells, and large output
driver cells. Noise generated in the low impedance output
drivers is isolated from the core logic and buffer areas. The
distribution of the supply rails can be automatically positioned
by the layout software which allows greater design flexibility
and optimisation.
separate pad locations or combined at a single location. All
I/O cell pads may be configured as either power or ground,
giving complete flexibility to the designer.
Process Technology
•
•
•
Operation outside these absolute maximum ratings may
permanently damage device characteristics and may affect
Supply Voltage
Input Voltage
Output Voltage
ESD protection
Current per pad
Storage Temperature
Ceramic
Plastic
Three power rings for good noise immunity
Optimized for efficient routing
User defined placement of Power and Ground pads
The power supply distribution scheme for the CLA70000
The power supply rings may be connected either to
Advanced 1 micron twin well process with epitaxial
substrate
Class 10 six inch wafer fabrication facility
High density low power process
Parameter
Absolute Maximum Ratings
-0.5
-0.5
-0.5
-65
-40
2.0
Min
Vdd + 0.5
Vdd + 0.5
100
150
125
Max
7.0
K Volts
Units
mA
C
C
V
V
V
Semiconductor 1 micron drawn CMOS process, which is the
third generation of our ‘V’ series process family. Manufacture
is at Class10, 6-inch fabrication facility. The process is a twin
well, self aligned oxide-isolated technology on an epitaxial
substrate, with an effective channel length of 0.8 micron,
giving low defect density, high reliability, and inherently low
power dissipation. The process has excellent immunity to
latchup, and ESD, and exhibits stable performance
characteristics ideal for all commercial, industrial and military
applications.
* 125 C maximum junction temperature for plastic devices.
**Subject to a maximum junction temperature of 150 C for
ceramic devices.
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Commercial Grade
Industrial Grade
Military Grade
The CLA70000 arrays are built using the Zarlink
Parameter
Recommended Maximum Operating Limits
Figure 3 - Power Supply Organisation
CLA70000 Series
Vss
Vss
-40
-55
3.0
Min
0
Vdd
Vdd
125**
Max
5.5
70
85*
VSS }
VDD }
VDD }
VSS }
Supply to
Core Logic
Supply to
Intermediate
Buffers
Supply to
I/O Buffers
Units
V
V
V
C
C
C
3