NJU6676 New Japan Radio Co., Ltd., NJU6676 Datasheet - Page 30

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NJU6676

Manufacturer Part Number
NJU6676
Description
64-Common x 132-Segment plus 1-Icon Bit Map Type LCD Controller and Driver
Manufacturer
New Japan Radio Co., Ltd.
Datasheet
(5-4) Serial Interface.(P/S="L")
Serial interface circuits consist of 8 bits shift register and 3 bits counter. SI and SCL input are
activated when the chip select terminal CS1 set to "L"and P/S terminal set to "L". The 8 bits shift
register and 3 bits counter are reset to the initial condition when the chip is not selected. The data
input from SI terminal is MSB first like as the order of D7,D6,- - - - D0, and the data are entered into
the shift register synchronizing with the rise edge of the serial clock SCL. The data in the shift
register are converted to parallel data at the 8th serial clock rise edge input. Discrimination of the
display data or instruction of the serial input data is executed by the condition of A0 at the 8th serial
clock rise edge. A0="H" is display data and A0="L" is instruction. When RES terminal becomes "L"
or CS1 terminal becomes "H" before 8th serial clock rise edge, NJU6676 recognizes them as a
instruction data incorrectly. Therefore a unit of serial data must be structured by 8-bit. The time chart
for the serial interface is shown in Fig. 5. To avoid the noise trouble, the short wiring is required for
the SCL input.
interface
Note) The read out function, such as the status or RAM data read out, is not supported in this serial
CS1
CS2
SCL
A0
SI
1
D7
2
D6
3
D5
4
D4
Fig.5
5
D3
6
D2
7
D1
8
D0
PRELIMINARY
NJU6676
9
D7
10
D6

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