AD9516-5 Analog Devices, Inc., AD9516-5 Datasheet - Page 48
AD9516-5
Manufacturer Part Number
AD9516-5
Description
14-output Clock Generator
Manufacturer
Analog Devices, Inc.
Datasheet
1.AD9516-5.pdf
(76 pages)
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AD9516-5
Table 45. Serial Control Port Timing
Parameter
t
t
t
t
t
t
t
t
DS
DH
CLK
S
C
HIGH
LOW
DV
SCLK
SDIO
CS
Description
Setup time between data and the rising edge of SCLK
Hold time between data and the rising edge of SCLK
Period of the clock
Setup time between the CS falling edge and the SCLK rising edge (start of communication cycle)
Setup time between the SCLK rising edge and the CS rising edge (end of communication cycle)
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
SCLK to valid SDIO and SDO (see Figure 54)
t
t
DS
S
BIT N
t
HIGH
t
DH
Figure 56. Serial Control Port Timing—Write
t
CLK
t
Rev. 0 | Page 48 of 76
LOW
BIT N + 1
t
C
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