LTC1410 Linear Technology, LTC1410 Datasheet
LTC1410
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LTC1410 Summary of contents
Page 1
... Two digitally selectable power shut- down modes provide flexibility for low power systems. The LTC1410’s full-scale input range is 2.5V. Maximum DC specifications include 1LSB INL and 1LSB DNL over temperature. Outstanding AC performance includes 71dB S/( and 82dB THD at the Nyquist input frequency of 625kHz ...
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... Analog Input Voltage (Note 3) .................................. V SS Digital Input Voltage (Note 4) ............ V Digital Output Voltage ................... – 0. Power Dissipation ............................................. 500mW Operating Temperature Range LTC1410C .............................................. LTC1410I ........................................... – Storage Temperature Range ................ – 150 C Lead Temperature (Soldering, 10 sec)................. 300 VERTER C HARA TERISTICS ...
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... V OUT DD The denotes specifications which apply over the full operating temperature range, CONDITIONS (Notes 10, 11) (Note 10 CONVST = 5V SHDN = 0V, NAP/SLP = 5V SHDN = 0V, NAP/SLP = CONVST = 5V SHDN = 0V, NAP/SLP = 5V SHDN = 0V, NAP/SLP = 0V LTC1410 MIN TYP MAX 70 72.5 68 71.0 – 85 – 82 – 74 – 84 – 74 – ...
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... LTC1410 W U POWER REQUIRE E TS otherwise specifications are (Note 5) A SYMBOL PARAMETER P Power Dissipation D Nap Mode Sleep Mode CHARACTERISTICS range, otherwise specifications are at T SYMBOL PARAMETER f Maximum Sampling Frequency SAMPLE(MAX) t Conversion Time CONV t Acquisition Time ACQ t Throughput Time ...
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... V = 0.1V RIPPLE –20 –40 – – DGND –100 –120 1k 10k 100k 1M 10M RIPPLE FREQUENCY (Hz) 1410 G08 LTC1410 Distortion vs Input Frequency 0 –10 –20 –30 –40 –50 –60 THD 3RD –70 –80 2ND –90 –100 1k 10k 100k 1M 10M INPUT FREQUENCY (Hz) ...
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... Positive Supply. Bypass to AGND DD with 10 F tantalum in parallel with 0.1 F ceramic SAMPLE C SAMPLE 12-BIT CAPACITIVE DAC SUCCESSIVE APPROXIMATION REGISTER INTERNAL CONTROL LOGIC CLOCK NAP/SLP SHDN CONVST ZEROING SWITCHES COMP – 12 D11 • OUTPUT LATCHES • • D0 BUSY LTC1410 • BD ...
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... U U APPLICATIONS INFORMATION CONVERSION DETAILS The LTC1410 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 12-bit parallel output. The ADC is complete with a precision reference and an internal clock. The control logic provides easy interface to microproces- sors and DSPs. (Please refer to the Digital Interface section for the data format ...
Page 8
... S/( the equation: = 1.25MHz N = [S/( – 1.76] where N is the effective number of bits of resolution and S/( expressed in dB. At the maximum sampling rate of 1.25MHz the LTC1410 maintains very good ENOBs up to the Nyquist input frequency of 625kHz and beyond. Refer to Figure 3. 500 600 1410 F02a Figure 3 ...
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... S/( does not become dominated by distortion until frequen- cies far beyond Nyquist. Driving the Analog Input The differential analog inputs of the LTC1410 are easy to drive. The inputs may be driven differentially single-ended input (i.e., the – and – ...
Page 10
... LT 1360, LT1220, LT1223, LT1224 and LT1227 op amps. The noise and the distortion of the input amplifier must also be considered since they will add to the LTC1410 noise and distortion. The small-signal bandwidth of the sample-and-hold circuit is 20MHz. Any noise that is present at the analog inputs will be summed over this entire bandwidth ...
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... Figure 8b. Using the LT1019-2 External Reference Full-Scale and Offset Adjustment Figure 9 shows the ideal input/output characteristics for the LTC1410. The code transitions occur midway between successive integer LSB values (i.e., – 0.5LSB, – 1.5LSB, – 2.5LSB – 1.5LSB, FS – 0.5LSB).The output is two’s complement binary with 1LSB = [(+FS) – ...
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... The LTC1410 has differential inputs to minimize noise coupling. Common mode noise on the + A leads will be rejected by the input CMRR. The – A can be used as a ground sense for the + A LTC1410 will hold and convert the difference voltage between + A and – The leads (Pin 2) should be kept as short as possible ...
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... U APPLICATIONS INFORMATION Power Shutdown The LTC1410 provides two power shutdown modes, Nap and Sleep, to save power during inactive periods. The Nap mode reduces the power by 95% and leaves only the digital logic and reference powered up. The wake-up time from Nap to active is 200ns. In Sleep mode all bias currents are shut down and only leakage current re- mains – ...
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... LTC1410 U U APPLICATIONS INFORMATION CONVST BUSY DATA Figure 14. Mode 1a. CONVST Starts a Conversion. Data Outputs Always Enabled (CONVST = CONVST BUSY DATA (N – 1) DATA DB11 TO DB0 Figure 15. Mode 1b. CONVST Starts a Conversion. Data Outputs Always Enabled (CONVST = CONVST BUSY RD DATA Figure 16. Mode 2. CONVST Starts a Conversion. Data is Read by RD ...
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... DWG # 05-08-1640 – 8 0.0256 (0.65) BSC 0.010 – 0.015 (0.25 – 0.38) LTC1410 DATA N DATA ( DB11 TO DB0 DB11-DB0 1410 F17 DATA N DB11 TO DB0 1410 F18 0.397 – 0.407* (10.07 – 10.33 0.301 – ...
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... LTC1410 PACKAGE DESCRIPTIO 0.291 – 0.299** (7.391 – 7.595) 0.010 – 0.029 45 (0.254 – 0.737) 0.009 – 0.013 NOTE 1 (0.229 – 0.330) 0.016 – 0.050 (0.406 – 1.270) NOTE: 1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. ...