RM5261-200-QI PMC-Sierra Inc, RM5261-200-QI Datasheet - Page 21

• Manufacturer Part Number: RM5261-200-QI
• Description: RM5261 Microprocessor with 64-Bit System Bus Data Sheet Released
• Manufacturer: PMC-Sierra Inc

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002241, Issue 1
3.20 Write buffer
3.21 System Interface
3.22 System Address/Data Bus
3.23 System Command Bus
Writes to external memory, whether cache miss write-backs or stores to uncached or write-through
addresses, use the on-chip write buffer. The write buffer holds up to four 64-bit address and data
pairs. The entire buffer is used for a data cache write-back and allows the processor to proceed in
parallel with the memory update. For uncached and write-through stores, the write buffer
significantly increases performance by decoupling the SysAD bus transfers from the instruction
execution stream.
The system interface consists of a 64-bit Address/Data bus with 8 parity check bits and a 9-bit
command bus. In addition, there are 6 handshake signals and 6 interrupt inputs. The interface is
capable of transferring data between the processor and memory at a peak rate of 800 MB/sec with
a 100 MHz SysClock.
Figure 6 shows a typical embedded system using the RM5261. In this example, a bank of DRAMs
and a memory controller ASIC share the processor’s SysAD bus while the memory controller
provides separate ports to a boot ROM and an I/O system.
Figure 6 Typical Embedded System Block Diagram
The 64-bit System Address Data (SysAD) bus is used to transfer addresses and data between the
RM5261 and the rest of the system. It is protected with an 8-bit parity check bus (SysADC). The
system interface is configurable to allow easy interfacing to memory and I/O systems of varying
frequencies.
The Block Write data rate, Non-block Write protocol, and Output Drive Strength are
programmable at Boot time via the Mode Control bits. The rate at which the processor receives
data is fully controlled by the external device.
The RM5261 interface has a 9-bit System Command (SysCmd) bus. The command bus indicates
whether the SysAD bus carries address or data information on a per-clock basis. If the SysAD
RM5261
DRAM
Latch
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RM5261™ Microprocessor with 64-Bit System Bus Data Sheet
Address
Control
Memory I/O
Controller
Flash/
Boot
Rom
8
x
PCI Bus
x
Released
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