spd6722qcce Intel Corporation, spd6722qcce Datasheet - Page 28
spd6722qcce
Manufacturer Part Number
spd6722qcce
Description
Isa-to-pc-card Pcmcia Controllers
Manufacturer
Intel Corporation
Datasheet
1.SPD6722QCCE.pdf
(138 pages)
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PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
28
Memory
Window Option
Enabled
Start Address
End Address
Offset Address
Data Size
Timing
Register Access
Setting
Write Protect
I/O
Window Option
Enabled
Start Address
End Address
Offset Address
Auto Size
Data Size
Timing
Caution: The windows of the PD67XX should never be allowed to overlap with each other or the other
Having five memory windows per socket allows a memory-type card to be accessed through four
memory windows programmed for common memory access (allowing PC-type expanded-
memory-style management), leaving the fifth memory window available to be programmed to
access the card’s attribute memory without disrupting the common memory in use.
Each of the five memory windows has several programming options, including:
Each of the two I/O windows has several programming options, including:
devices in the system. This would cause collisions in the IOCS16*, MEMCS16*, IOCHRDY, and
SD[15:0] signals, resulting in erratic behavior.
Description
Each of the five memory windows can be individually enabled. Disabled windows are not responded to.
The starting address of the window is programmable on 4-Kbyte boundaries starting at 64 Kbytes
(1000h) with a maximum address of 16 Mbyte.
The ending address of the window is programmable on 4-Kbyte boundaries starting at 64 Kbytes
(1000h) with a maximum address of 16 Mbyte. Only memory accesses between the starting and ending
address are responded to.
The offset address is added to the ISA address to determine the address for accessing the PC Card.
This allows the addresses in the PC Card address space to be different from the ISA address space.
The size of accesses can be set manually to either 8 or 16 bits.
The timing of accesses (Setup/Command/Recovery) can be set by either of two timing register sets:
Timer Set 0 or Timer Set 1.
The -REG pin can be enabled on a per-window basis so that any of the windows can be used for
accessing attribute memory.
If the window is programmed to be write-protected, then writes to the memory window are ignored (reads
are still performed normally).
Description
Each of the two I/O windows can be individually enabled.
The starting address of the window is programmable on single-byte boundaries from 0 to 64 Kbytes.
The ending address of the window is also programmable on single-byte boundaries from 0 to 64 Kbytes.
The offset address is added to the ISA address to determine the address for accessing the PC Card.
The size of accesses can be set automatically, based on the PC Card -IOIS16 signal.
The size of accesses can be set manually to either 8 or 16 bits, overriding the Auto Size option.
The timing of accesses (Setup/Command/Recovery) can be set by either of two timing register sets:
Timer Set 0 or Timer Set 1.
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