upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 237
upd78f9211grt2-jjg-a
Manufacturer Part Number
upd78f9211grt2-jjg-a
Description
8-bit Single-chip Microcontrollers
Manufacturer
ETC-unknow
Datasheet
1.UPD78F9211GRT2-JJG-A.pdf
(352 pages)
- Current page: 237 of 352
- Download datasheet (3Mb)
16.8.6 Example of block erase operation in self programming mode
An example of the block erase operation in self programming mode is explained below.
<1> Set 03H (block erase) to the flash program command register (FLCMD).
<2> Set the block number to be erased, to flash address pointer H (FLAPH).
<3> Set flash address pointer L (FLAPL) to 00H.
<4> Write the same value as FLAPH to the flash address pointer H compare register (FLAPHC).
<5> Set the flash address pointer L compare register (FLAPLC) to 00H.
<6> Clear the flash status register (PFS).
<7> Write ACH to the watchdog timer enable register (WDTE) (clear and restart the watchdog timer counter)
<8> Execute the HALT instruction then start self programming. (Execute an instruction immediately after the
<9> Check if a self programming error has occurred using bit 1 (VCERR) and bit 2 (WEPRERR) of PFS.
<10> Block erase processing is abnormally terminated.
<11> Block erase processing is normally terminated.
Note This setting is not required when the watchdog timer is not used.
HALT instruction if self programming has been executed.)
Abnormal → <10>
Normal
→ <11>
CHAPTER 16 FLASH MEMORY
User’s Manual U16994EJ3V0UD
Note
237
.
Related parts for upd78f9211grt2-jjg-a
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
Manufacturer:
ETC-unknow
Datasheet:
Part Number:
Description:
Manufacturer:
ETC-unknow
Datasheet: