upd78f9211grt2-jjg-a ETC-unknow, upd78f9211grt2-jjg-a Datasheet - Page 271

• Manufacturer Part Number: upd78f9211grt2-jjg-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: ETC-unknow

Remark
SUBC
AND
OR
XOR
Mnemonic
One instruction clock cycle is one CPU clock cycle (f
(PCC).
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
Operand
CHAPTER 17 INSTRUCTION SET OVERVIEW
Bytes
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
User’s Manual U16994EJ3V0UD
Clocks
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
(saddr), CY ← (saddr) − byte − CY
A, CY ← A − r − CY
A, CY ← A − (HL) − CY
(saddr) ← (saddr) ∧ byte
A ← A ∧ r
A ← A ∧ (HL)
(saddr) ← (saddr) ∨ byte
A ← A ∨ r
A ← A ∨ (HL)
(saddr) ← (saddr) ∨ byte
A ← A ∨ r
A ← A ∨ (HL)
A, CY ← A − byte − CY
A, CY ← A − (saddr) − CY
A, CY ← A − (addr16) − CY
A, CY ← A − (HL + byte) − CY
A ← A ∧ byte
A ← A ∧ (saddr)
A ← A ∧ (addr16)
A ← A ∧ (HL + byte)
A ← A ∨ byte
A ← A ∨ (saddr)
A ← A ∨ (addr16)
A ← A ∨ (HL + byte)
A ← A ∨ byte
A ← A ∨ (saddr)
A ← A ∨ (addr16)
A ← A ∨ (HL + byte)
CPU
) selected by the processor clock control register
Operation
Z
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
Flag
AC CY
×
×
×
×
×
×
×
271
×
×
×
×
×
×
×