upd78f0103 Renesas Electronics Corporation., upd78f0103 Datasheet - Page 243

• Manufacturer Part Number: upd78f0103
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

(6) Asynchronous serial interface control register 6 (ASICL6)
Address: FF58H After reset: 16H R/W
ASICL6
Note Bits 2 to 5 and 7 are read-only.
Cautions 1. In the case of an SBF reception error, return the mode to the SBF reception mode again. The
Symbol
This register controls the serial communication operations of serial interface UART6.
ASICL6 can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 16H.
Caution ASICL6 can be refreshed (the same value is written) by software during a communication
2. Before setting the SBRT6 bit, make sure that bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1.
3. The read value of the SBRT6 bit is always 0. SBRT6 is automatically cleared to 0 after SBF
4. Before rewriting the DIR6 and TXDLV6 bits, clear the TXE6 and RXE6 bits to 0.
Figure 12-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6)
operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5
(RXE6) of ASIM6 = 1). Note, however, that communication is started by the refresh operation
because bit 6 (SBRT6) of ASICL6 is cleared to 0 when communication is completed (when an
interrupt signal is generated).
TXDLV6
SBRF6
SBRF6
SBRT6
DIR6
status of the SBRF6 flag is held (1).
reception has been correctly completed.
<7>
0
1
0
1
0
1
0
1
If POWER6 = 0 and RXE6 = 0 or if SBF reception has been completed correctly
SBF reception in progress
SBF reception trigger
MSB
LSB
Normal output of T
Inverted output of T
SBRT6
<6>
Note
CHAPTER 12 SERIAL INTERFACE UART6
X
D6
X
5
0
D6
User’s Manual U15836EJ5V0UD
Enables/disables inverting T
4
1
SBF reception status flag
SBF reception trigger
First bit specification
3
0
X
D6 output
2
1
DIR6
1
TXDLV6
0
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