sc9822p Silan, sc9822p Datasheet - Page 26

• Manufacturer Part Number: sc9822p
• Description: Mp3 Decoder With Esp Function And Cd Interface
• Manufacturer: Silan

1. Interface to main control MCU
ATTACHMENT
INTERFACE FUNCTION DESCRIPTION
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
Http: www.silan.com.cn
company.
1.1 Serial interface signal form
sequence is as followed:
1. 2 Serial communication protocol processing
the data. The transmission process of one frame is as followed:
(as long as the wave is not distortion), and is independent with Guest port; DataAvail used for marking
effective data time quantum is also sent by host computer and it is a low active; Data is a bidirectional signal
with pull-up resistor and used for specific data communication and feedback. As above picture, the data sent
by the host port is all at the falling edge of SsiSClk and the feedback data or Ack signal of guest port are at
the rising edge. We define one transmitting process as a frame, and the details of the coherent signal are as
followed:
Start Signal:
Data Signal:
Ack:
EndSignal:
SC9822P communicates with host computer’ s MCU in synchronism serial bus (SSI) data interface of our
The serial interface communicating with MCU has 3 signal lines including control signal, data signal, and the
Host and Guest realize the communication between each other by different explanation and processing for
Thereinto, SsiSClk is the clock generating from Host port, and the frequency can rebound in a wide range
Start of frame
We define the first checking low level of DataAvail at the rising edge of SsiSClk at Guest
port as the start of frame. When check the start signal, the guest can receive the data at
the next rising edge.
Data signal
Data signal bit wide sent by host computer is one SsiSClk clock cycle.
Feedback signal
1. When Guest port receives the right addressing data, it feeds back to Host signal. And
2. When Host sends to all Guest ports, signal before sending data is as lead signal, and
End of frame
When Guest detects the DataAvail at rising edge of SsiSClk, it means the transmission is
end and waits for the next one.
between two falling edges of SsiSClk.
the width is a SsiSClk cycle. Used for data lead avoiding unmatched signal between two
rising edges or corresponding to the data feedback to Host.
REV:1.0
SC9822P
Page 26 of 30
2006.07.21