t6020m ATMEL Corporation, t6020m Datasheet - Page 10

• Manufacturer Part Number: t6020m
• Description: Low-current Microcontroller For Watchdog Function
• Manufacturer: ATMEL Corporation

Interrupt Processing
For processing the eight interrupt levels, the MARC4
includes an interrupt controller with two 8-bit wide
”interrupt pending” and ”interrupt active” registers. The
interrupt controller samples all interrupt requests during
every non-I/O instruction cycle and latches these in the
interrupt pending register. If no higher priority interrupt
is present in the interrupt active register, it signals the
CPU to interrupt the current program execution. If the
interrupt enable bit is set, the processor enters an interrupt
acknowledge cycle. During this cycle a short call
(SCALL) instruction to the service routine is executed
and the current PC is saved on the return stack. An
interrupt service routine is completed with the RTI
instruction. This instruction sets the interrupt enable flag,
resets
pending/active register and fetches the return address
from the return stack to the program counter. When the
interrupt enable flag is reset (triggering of interrupt
routines are disabled), the execution of new interrupt
T6020M
10 (54)
7
6
5
4
3
2
1
0
the
Main /
Autosleep
corresponding
INT3
INT3 active
INT5
bits
INT5 active
INT7
in
INT7 active
the
Figure 8. Interrupt handling
interrupt
RTI
INT2
Time
Ï Ï Ï Ï Ï Ï
Ï Ï Ï Ï Ï Ï
INT2 pending
service routines is inhibited but not the logging of the
interrupt requests in the interrupt pending register. The
execution of the interrupt is delayed until the interrupt
enable flag is set again. Note that interrupts are only lost
if an interrupt request occurs while the corresponding bit
in the pending register is still set (i.e., the interrupt service
routine is not yet finished).
It should also be noted that automatic stacking of the RBR
is not carried out by the hardware and so if ROM banking
is used, the RBR must be stacked on the expression stack
by the application program and restored before the RTI.
After a master reset (power-on, brown-out or watchdog
reset), the interrupt enable flag and the interrupt pending
and interrupt active register are all reset.
Interrupt Latency
The interrupt latency is the time from the occurrence of
the interrupt to the interrupt service routine being
activated. In MARC4 this is extremely short (taking
between 3 to 5 machine cycles depending on the state of
the core).
RTI
SWI0
Ï Ï Ï Ï Ï Ï
Ï Ï Ï Ï Ï Ï
INT0 pending
INT2 active
RTI
INT0 active
RTI
Rev. A3, 02-Apr-01
RTI
Main /
Autosleep
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