t6020m ATMEL Corporation, t6020m Datasheet - Page 40

• Manufacturer Part Number: t6020m
• Description: Low-current Microcontroller For Watchdog Function
• Manufacturer: ATMEL Corporation

9-bit Shift Mode (I
In the 9-bit shift mode, the SSI is able to handle the I
protocol (described below). It always operates as an I
master device, i.e., SC is always generated and output by
the SSI. Both the I
matically generated whenever the SSI is activated or
deactivated by the SIR–bit. In accordance with the I
protocol, the output data is always changed in the clock
low phase and shifted in on the high phase.
Before activating the SSI (SIR=0) and commencing an
I
word must be set using the SDD control bit. The state of
this bit controls the direction of the data port (BP43 or
MCL_SD). Once started, the 8 data bits are, depending on
the selected direction, either clocked into or out of the
shift register. During the 9th clock period, the port
direction is automatically switched over so that the
T6020M
40 (54)
2
C dialog, the appropriate data direction for the first
(IFN = 0)
(IFN = 1)
Interrupt
Interrupt
SRDY
ACT
(IFN = 0)
(IFN = 1)
SIR
Interrupt
Interrupt
SD
SC
SRDY
ACT
2
SIR
C start and stop conditions are auto-
SD
SC
msb
2
7 6 5
C compatible)
Write STB
(tx data 1)
rx data 1
4 3 2 1 0
Figure 42. Example of 8-bit synchronous transmit operation
Figure 43. Example of 8-bit synchronous receive operation
msb
7 6 5 4 3 2 1 0
lsb
tx data 1
msb
7 6 5
lsb
rx data 2
4 3 2 1 0
Write STB
(tx data 2)
2
2
2
C
C
C
lsb
msb
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
corresponding acknowledge bit can be shifted out or read
in. In transmit mode, the acknowledge bit received from
the slave device is captured in the SSI Status Register
(TACK ) where it can be read by the controller. and in
receive mode, the state of the acknowledge bit to be
returned to the slave device is predetermined by the SSI
Status Register (RACK ).
Changing the directional mode (TX/RX) should not be
performed during the transfer of an I
should wait until the end of the telegram which can be
detected using the SSI interrupt (IFN =1) or by
interrogating the ACT status.
A 9-bit telegram, once started will always run to
completion and will not be prematurely terminated by the
SIR bit. So, if the SIR–bit is set to ‘1’ in mit telegram, the
SSI will complete the current transfer and terminate the
dialog with an I
Write STB
(tx data 3)
tx data 2
Read SRB
(rx data 1)
lsb msb
msb
7 6 5 4 3 2 1 0
2
Read SRB
(rx data 2)
C stop condition.
rx data 3
tx data 3
lsb
lsb
Read SRB
(rx data 3)
7 6 5 4
Rev. A3, 02-Apr-01
13824
2
C telegram. One
13825