st52f510 STMicroelectronics, st52f510 Datasheet - Page 31

• Manufacturer Part Number: st52f510
• Description: 8-bit Intelligent Controller Unit Icu Two Timer/pwms, Adc, I2c, Spi, Sci
• Manufacturer: STMicroelectronics

4 MEMORY PROGRAMMING
ST52F510/F513/F514 provides an on-chip user
programmable non-volatile memory, which allows
fast and reliable storage of user data.
Program/Data Memory addressing space is
composed by a Single Voltage Flash Memory and
a RAM memory bench. The ST52F513/514
devices also have a Data EEPROM bench to store
permanent data with long term retention and a high
number of write/erase cycles.
All the Program Data memory addresses can
execute code, including RAM and EEPROM
benches.
The memory is programmed by setting the V
equal to V
through the I
same procedure is used to perform “In-Situ” the
programming of the device after it is mounted in
the user system. Data can also be written in run-
time with the In-Application Programming (IAP).
The Memory can be locked by the user during the
programming phase, in order to prevent external
operation such as reading the program code and
assuring protection of user intellectual property.
Flash and EEPROM pages can be protected by
unintentional writings.
Table 4.1 Sales Type Memory Organization
ST52F510c2p6
ST52F510c3p6
ST52F513c2p6
ST52F513c3p6
ST52F514c1p6
ST52F514c3p6
legend:
c:
p:
Y=16 pins, F=20 pins, G=28 pins, K=32/34 pin
B=DIP, M=SO, T=TQFP
Device
dd
. Data and commands are transmitted
2
C serial communication protocol. The
4096 bytes
8192 bytes
3840 bytes
7936 bytes
4096 bytes
4096 bytes
Amount
Flash Memory
0 to 15
0 to 31
0 to 14
0 to 30
0 to 15
0 to 15
Pages
pp
pin
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
Amount
Remark: the memory contents are protected by
the Error Correction Code (ECC) algorithm that
uses a 4-bit redundancy to correct one bit errors.
Warning: when entering the ISP, the default
values for Option Bytes are considered, so a
Voltage Supply higher than the PLVD lower
threshold must be applied to program the device.
4.1 Program/Data Memory Organization
The Program/Data Memory is organized as
described in Section 3.3. The various sales types
have different amounts of each type of memory.
Table 4.1 describes the memory benches amount
and page allocation for each sales type.
The addressing spaces are organized in pages of
256 bytes. Each page is composed by blocks of 32
bytes. Memory programming is performed one
block at a time in order to speed-up the
programming time (about 2.5 ms per block).
The whole location address is composed as
follows:
RAM Memory
15
Page address
Page
32
32
32
32
32
32
8
1024 bytes
4096 bytes
256 bytes
256 bytes
Amount
ST52F510/F513/F514
Block address address inside the block
7
EEPROM Memory
-
-
5
4
Page(s)
16-19
16-31
15
31
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-
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