mcf5282 Freescale Semiconductor, Inc, mcf5282 Datasheet - Page 232

• Manufacturer Part Number: mcf5282
• Manufacturer: Freescale Semiconductor, Inc

External Interface Module (EIM)
The write cycle timing diagram is shown in
Table 13-3
13.4.5
Two clock cycle transfers are supported on the external bus. In most cases, this is impractical to use in a
system because the termination must take place in the same half-clock during which TS is asserted. As this
is atypical, it is not referred to as the zero-wait-state case but is called the fast-termination case. Fast
termination cycles occur when the external device or memory asserts TA less than one clock after TS is
asserted. This means that the processor samples TA on the rising edge of the second cycle of the bus
transfer.
with internal termination.
Figure 13-10
13-8
Figure 13-9
A[31:0], SIZ[1:0]
A[31:0], SIZ[1:0]
CSn, BSn, OE
describes the six states of a basic write cycle.
Fast Termination Cycles
shows a write cycle with fast termination.
CSn, BSn
CLKOUT
CLKOUT
D[31:0]
D[31:0]
R/W
R/W
TIP
TIP
TS
TA
TS
TA
shows a read cycle with fast termination. Note that fast termination cannot be used
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Figure 13-9. Read Cycle with Fast Termination
Figure 13-8. Basic Write Bus Cycle
S0
Figure
S0
S1
Read
13-8.
S1
S4
S2
Write
S5
S3
S4
S5
Freescale Semiconductor