ics1893cy-10 Integrated Device Technology, ics1893cy-10 Datasheet - Page 112
ics1893cy-10
Manufacturer Part Number
ics1893cy-10
Description
3.3-v 10base-t/100base-tx Integrated Phyceiver
Manufacturer
Integrated Device Technology
Datasheet
1.ICS1893CY-10.pdf
(143 pages)
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8.3.4.3 MAC/Repeater Interface Pins for 10M Serial Interface
ICS1893CY-10 Rev 1/07
Table 8-7
Table 8-7. MAC/Repeater Interface Pins: 10M Serial Interface
COL
CRS
MDC
MDIO
RXCLK
RXD0
RXD1
RXD2
RXD3
MII Pin
Name
ICS1893CY-10 Data Sheet - Release
lists the MAC/Repeater Interface pin descriptions for the 10M Serial Interface.
10COL
10CRS
MDC
MDIO
10RCLK
10RD
–
Symbol
Name
100M
Pin
No.
Pin
49
50
31
30
38
35
34
33
32
Copyright © 2007, Integrated Device Technology, Inc.
Connect
Output
Output
Output
Output
Input/
Type
Input
Pin
No
10M (Serial Interface) Collision (Detect).
This pin’s description is the same as that given in
10M (Serial Interface) Carrier Sense.
This pin’s description is the same as that given in
Management Data Clock.
This pin’s description is the same as that given in
Management Data Input/Output.
This pin’s description is the same as that given in
10M Receive Clock.
In 10M Serial mode, the ICS1893CY-10 sources the 10RCLK to
its MAC/repeater Interface. The 10RCLK synchronizes the data
on the 10RD0 pin between the ICS1893CY-10 and the
MAC/repeater.
10M (Serial Interface) Receive Data 0.
This pin’s description is the same as that given in
Receive Data 1–3.
For the 10M Serial Interface, these pins are a no connect. For
more information, see
All rights reserved.
•
•
•
•
Note: The signal on the 10RCLK pin is conditioned by the
The 10RCLK frequency is 10 MHz.
The ICS1893CY-10 generates 10RCLK from the MDI data
stream using a digital PLL. When the MDI data stream
terminates, the PLL continues to operate, synchronously
referenced to the last packet received.
The ICS1893CY-10 switches between clock sources during
the period between when 10CRS is being asserted and
10RXDV is being asserted. While the ICS1893CY-10 locks
onto the incoming data stream, a clock phase change of up
to 360 degrees can occur.
The 10RCLK aligns once per packet.
112
RXTRI pin.
Chapter 8 Pin Diagram, Listings, and Descriptions
Table
Pin Description
5-2.
Table
Table
Table
Table
Table
8-5.
8-5.
8-5.
8-5.
8-5.
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