adv7390 Analog Devices, Inc., adv7390 Datasheet - Page 60

• Manufacturer Part Number: adv7390
• Description: Low Power, Chip Scale 10-bit Sd/hd Video Encoder
• Manufacturer: Analog Devices, Inc.

ADV7390/ADV7391/ADV7392/ADV7393
EXTERNAL HORIZONTAL AND VERTICAL SYNCHRONIZATION CONTROL
For timing synchronization purposes, the ADV739x is able to accept either EAV/SAV time codes embedded in the input pixel data or
external synchronization signals provided on the HSYNC and VSYNC pins (see Table 48). It is also possible to output synchronization
signals on the HSYNC and VSYNC pins (see Table 49 to Table 51).
Table 48. Timing Synchronization Signal Input Options
Signal
SD HSYNC In
SD VSYNC/FIELD In
ED/HD HSYNC In
ED/HD VSYNC/FIELD In
1
Table 49. Timing Synchronization Signal Output Options
Signal
SD HSYNC Out
SD VSYNC/FIELD Out
ED/HD HSYNC Out
ED/HD VSYNC/FIELD Out
1
2
Table 50. HSYNC Output Control
ED/HD Input Sync
Format (0x30, Bit 2)
x
x
0
1
x
1
Table 51. VSYNC Output Control
ED/HD Input
Sync Format
(0x30, Bit 2)
x
x
0
1
1
x
x
1
SD and ED/HD timing synchronization outputs must also be disabled (Subaddress 0x02[7:6] = 00).
ED/HD timing synchronization outputs must also be disabled (Subaddress 0x02, Bit 7 = 0).
ED/HD timing synchronization inputs must also be disabled, that is, embedded EAV/SAV timing codes must be enabled (Subaddress 0x30, Bit 2 = 1).
In all ED/HD standards where there is a HSYNC output, the start of the HSYNC pulse is aligned with the falling edge of the embedded HSYNC in the output video.
In all ED/HD standards where there is a VSYNC output, the start of the VSYNC pulse is aligned with the falling edge of the embedded VSYNC in the output video.
ED/HD VSYNC
Control
(0x34, Bit 2)
x
x
0
0
0
1
1
ED/HD HSYNC
Control
(0x34, Bit 1)
x
x
0
0
1
Pin
HSYNC
VSYNC
HSYNC
VSYNC
Pin
HSYNC
VSYNC
HSYNC
VSYNC
ED/HD Sync
Output Enable
(0x02, Bit 7)
0
0
1
1
1
1
1
1
1
ED/HD Sync
Output Enable
(0x02, Bit 7)
0
0
1
1
1
Condition
SD Slave Timing Mode 1, Mode 2, or Mode 3 Selected (Subaddress 0x8A[2:0]).
SD Slave Timing Mode 1, Mode 2, or Mode 3 Selected (Subaddress 0x8A[2:0]).
ED/HD Timing Synchronization Inputs Enabled (Subaddress 0x30, Bit 2 = 0).
ED/HD Timing Synchronization Inputs Enabled (Subaddress 0x30, Bit 2 = 0).
Condition
SD Timing Synchronization Outputs enabled (Subaddress 0x02, Bit 6 = 1).
SD Timing Synchronization Outputs enabled (Subaddress 0x02, Bit 6 = 1).
ED/HD Timing Synchronization Outputs enabled (Subaddress 0x02, Bit 7 = 1).
ED/HD Timing Synchronization Outputs enabled (Subaddress 0x02, Bit 7 = 1).
SD Sync
Output Enable
(0x02, Bit 6)
0
1
x
x
x
x
x
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SD Sync
Output Enable
(0x02, Bit 6)
0
1
x
x
x
Video Standard
x
Interlaced
x
All HD interlaced
standards
All ED/HD progressive
standards
All ED/HD standards
except 525p
525p
Signal on HSYNC Pin
Tristate.
Pipelined SD HSYNC.
Pipelined ED/HD HSYNC.
Pipelined ED/HD HSYNC based on
AV Code H bit.
Pipelined ED/HD HSYNC based on
horizontal counter.
Signal on VSYNC Pin
Tristate.
Pipelined SD VSYNC/Field.
Pipelined ED/HD VSYNC
or field signal.
Pipelined Field signal
based on AV Code F bit.
Pipelined VSYNC based on
AV Code V bit.
Pipelined ED/HD VSYNC
based on vertical counter.
Pipelined ED/HD VSYNC
based on vertical counter.
1
1
1
1
Duration
–
See Error! Reference
source not found..
As per HSYNC timing.
Same as line blanking
interval.
Same as embedded
HSYNC.
2
2
Duration
–
See Error!
Reference source
not found..
As per VSYNC or
Field signal timing.
Field.
Vertical blanking
interval.
Aligned with
serration lines.
Vertical blanking
interval.