adv7390 Analog Devices, Inc., adv7390 Datasheet - Page 86
![no-image](/images/no-image-200.jpg)
adv7390
Manufacturer Part Number
adv7390
Description
Low Power, Chip Scale 10-bit Sd/hd Video Encoder
Manufacturer
Analog Devices, Inc.
Datasheet
1.ADV7390.pdf
(96 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
adv7390BCPZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Company:
Part Number:
adv7390BCPZ-REEL
Manufacturer:
LT
Quantity:
1 000
Company:
Part Number:
adv7390WBCPZ
Manufacturer:
AD
Quantity:
101
ADV7390/ADV7391/ADV7392/ADV7393
Table 67. 10-Bit 525i YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x80
0x82
0x88
Table 68. 10-Bit 525i YCrCb In, RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x80
0x82
0x88
0x8A
Table 69. 16-Bit 525i YCrCb In, YPrPb Out
Subaddress
0x17
0x00
0x01
0x80
0x82
0x88
0x8A
Setting
0x02
0x1C
0x00
0x10
0x10
0xC9
0x10
Setting
0x02
0x1C
0x00
0x10
0x10
0xC9
0x10
0x0C
Setting
0x02
0x1C
0x00
0x10
0xC9
0x08
0x0C
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
RGB output enabled. RGB output sync
enabled.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
10-bit input enabled.
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
RGB output enabled. RGB output sync
enabled.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
10-bit input enabled.
Timing Mode 2 (Slave). HSYNC/VSYNC
synchronization.
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled. pedestal enabled.
16-bit input enabled.
Timing Mode 2 (Slave). HSYNC / VSYNC
synchronization.
Rev. 0 | Page 86 of 96
Table 70. 16-Bit 525i YCrCb In, RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x80
0x82
0x88
0x8A
Table 71. 16-Bit 525i RGB In, YPrPb Out
Subaddress
0x17
0x00
0x01
0x80
0x82
0x87
0x88
0x8A
Table 72. 16-Bit 525i RGB In, CVBS/Y-C Out
Subaddress
0x17
0x00
0x01
0x80
0x82
0x87
0x88
0x8A
Setting
0x02
0x1C
0x00
0x10
0x10
0xC9
0x08
0x0C
Setting
0x02
0x1C
0x00
0x10
0xC9
0x80
0x08
0x0C
Setting
0x02
0x1C
0x00
0x10
0xCB
0x80
0x08
0x0C
Description
Software reset
All DACs enabled. PLL enabled (16×).
SD input mode.
RGB output enabled. RGB output sync
enabled.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
16-bit input enabled.
Timing Mode 2 (Slave). HSYNC/VSYNC
synchronization.
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
RGB input enabled.
16-bit input enabled.
Timing Mode 2 (Slave). HSYNC/VSYNC
synchronization.
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. CVBS/S-Video out. SSAF
PrPb filter enabled. Active video edge
control enabled. Pedestal enabled.
RGB input enabled.
16-bit input enabled.
Timing Mode 2 (Slave). HSYNC/VSYNC
synchronization.