adsp-21991 Analog Devices, Inc., adsp-21991 Datasheet - Page 28

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adsp-21991

Manufacturer Part Number
adsp-21991
Description
Mixed Signal Dsp Controller
Manufacturer
Analog Devices, Inc.
Datasheet

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ADSP-21991
External Port Bus Request/Grant Cycle Timing
Table 10
bus grant operations.
Table 10. External Port Bus Request and Grant Cycle Timing
1
2
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
t
These are timing parameters that are based on worst-case operating conditions.
BS
BH
SD
SE
DBG
EBG
DBH
EBH
HCLK
is the peripheral clock period.
and
CLKOUT
1, 2
Figure 11
MS3--0
A21–0
IOMS
BGH
BMS
CLKOUT High to BR Deasserted Hold Time
CLKOUT High to xMS, Address, and RD/WR Disable
CLKOUT Low to xMS, Address, and RD/WR Enable
CLKOUT High to BG Asserted Setup
CLKOUT High to BG Deasserted Hold Time
CLKOUT High to BGH Asserted Setup
CLKOUT High to BGH Deasserted Hold Time
BR
BR Asserted to CLKOUT High Setup
WR
RD
BG
describe external port bus request and
t
BS
Figure 11. External Port Bus Request and Grant Cycle Timing
t
BH
–28–
t
t
t
t
t
DBG
DBH
SD
SD
SD
Min
4.6
0
0
0
0
0
0
Max
0.5t
4
4
4
4
4
HCLK
t
t
EBG
EBH
+1
t
t
t
SE
SE
SE
REV. 0
Unit
ns
ns
ns
ns
ns
ns
ns
ns

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