adsp-21469 Analog Devices, Inc., adsp-21469 Datasheet - Page 22

• Manufacturer Part Number: adsp-21469
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21469/ADSP-21469W
Clock Input
Table 14. Clock Input
1
2
3
Clock Signals
The ADSP-21469 can use an external clock or a crystal. See the
CLKIN pin description in
ure the ADSP-21469 to use its internal clock generator by
connecting the necessary components to CLKIN and XTAL.
Figure 6
operating in fundamental mode. Note that the clock rate is
achieved using a 28.125 MHz crystal and a PLL multiplier ratio
16:1 (CCLK:CLKIN achieves a clock speed of 450 MHz). To
achieve the full core clock rate, programs need to configure the
multiplier bits in the PMCTL register.
Parameter
Timing Requirements
t
t
t
t
t
Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in PMCTL.
Applies only for CLKCFG1–0 = 01 and default values for PLL control bits in PMCTL.
Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t
CK
CKL
CKH
CKRF
CCLK
CLKIN
3
Figure 6. 450 MHz Operation (Fundamental Mode Crystal)
shows the component connections used for a crystal
C1
22pF
R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL
DRIVE POWER. REFER TO CRYSTAL
MANUFACTURER’S SPECIFICATIONS
*TYPICAL VALUES
CLKIN
CLKIN Period
CLKIN Width Low
CLKIN Width High
CLKIN Rise/Fall (0.4 V to 2.0 V)
CCLK Period
28.125 MHz
Figure 5. Clock Input
t
CKH
R1
1M *
Table
Y1
ADSP-21469
6. The programmer can config-
XTAL
t
CK
t
R2
47 *
C2
22pF
CKL
Rev. PrB | Page 22 of 56 | November 2008
CCLK
450 MHz
Min
TBD
TBD
TBD
2.22
.
1
1
1
1
Preliminary Technical Data
Max
TBD
TBD
TBD
TBD
TBD
2
2
2
Unit
ns
ns
ns
ns
ns