dsp56853 Freescale Semiconductor, Inc, dsp56853 Datasheet - Page 34

• Manufacturer Part Number: dsp56853
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

34
IRQA, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction execution
in the interrupt service routine
IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine
IRQA Low to First Valid Interrupt Vector Address Out
recovery from Wait State
Delay from IRQA Assertion (exiting Stop) to External
Data Memory
Delay from IRQA Assertion (exiting Wait) to External
Data Memory
normal operation
internal reset mode
RSTO pulse width
Operating Conditions: V
1.
2.
3.
clock, t
4.
not the minimum required so that the IRQA interrupt is accepted.
5.
6.
requested (OMR bit 6 is set to 1). In both cases the PLL and the master clock are unaffected by stop mode entry. Recovery takes
one less cycle and t
7.
clock, recovery will take an extra cycle (to restart the clock), and t
8.
Fast
Normal
Table 4-8 Reset, Stop, Wait, Mode Select, and Interrupt Timing
6
In the formulas, T = clock cycle. For f
Parameters listed are guaranteed by design.
At reset, the PLL is disabled and bypassed. The part is then put into Run mode and t
The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is
The interrupt instruction fetch is visible on the pins only in Mode 3.
Fast stop mode:
Normal stop mode:
As a power saving feature, normal stop mode disables and bypasses the PLL. Stop mode will then shut down the master
ET = External Clock period, For an external crystal frequency of 8MHz, ET=125 ns.
Fast stop recovery applies when external clocking is in use (direct clocking to XTAL) or when fast stop mode recovery is
xtal
7
, t
5
extal
or t
8
Characteristic
osc
clk
SS
.
will continue same value it had before stop mode was entered.
= V
4
SSIO
= V
SSA
= 0 V, V
op
= 120MHz operation and f
DD
56853 Technical Data, Rev. 6
= 1.62-1.98V, V
t
Symbol
t
IDM -FAST
t
IRI -FAST
DDIO
IG -FAST
t
RSTO
t
clk
t
IDM
t
t
t
IRI
IW
IG
IF
will resume at the input clock source rate.
= V
ipb
DDA
= 60MHz, T = 8.33ns.
= 3.0–3.6V, T
128ET
22ET
1.5T
8ET
18T
14T
18T
14T
22T
18T
18T
Min
A
= –40° to +120°C, C
clk
Max
—
—
—
—
—
—
—
—
—
—
—
assumes the period of the source
1, 2 (Continued)
Unit
Freescale Semiconductor
ns
ns
ns
ns
ns
ns
—
—
L
≤ 50pF, f
See Figure
op
= 120MHz
4-13
4-13
4-14
4-15
4-15
4-16