xc5vlx330 Xilinx Corp., xc5vlx330 Datasheet

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... READY_WAIT signal that synchronizes the start of the FPGA configuration process, improving both system reliability and simplifying board design. Platform Flash XL can download an XC5VLX330 bitstream (79,704,832 bits) in less than 100 ms, making the configuration performance of Platform Flash XL ideal for Virtex-5 FPGA Endpoint solutions for PCI Express and other high-performance applications ...

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R X-Ref Target - Figure 1 Platform Flash XL READY_WAIT FPGA Design (.bit) File Figure 1: Platform Flash XL Delivers Reliable, High-Performance FPGA Configuration used to hold general purpose data or embedded processor code. Platform Flash XL integrates well with ...

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R Flash Memory Architecture Overview Platform Flash 128- × 16) non-volatile flash memory. The device is in-system programmable with a 1.8V core (V ) power supply. A separate I enables I/O operation at ...

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R X-Ref Target - Figure 4 Parameter DS617 (v2.1) May 14, 2008 Preliminary Product Specification Platform Flash XL High-Density Storage and Configuration Device 7FFFFFh 16 Kword 7FC000h 7F3FFFh 16 Kword 7F0000h Bank 7EFFFFh 64 Kword 7E0000h 78FFFFh 64 Kword 780000h ...

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R Pinout and Signal Descriptions See Figure 5 and Table 2 for a logic diagram and brief overview of the signals connected to this device. Table 2: Signal Names Signal Name Function A0-A22 Address Inputs Data Input/Outputs, DQ0-DQ15 Command Inputs ...

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R X-Ref Target - Figure DQ8 DQ1 F K DQ0 G A22 Figure 6: FT64 Package Connections (Top View ...

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R During Write operations, L can be tied Low (V addresses to flow through. Table 3: Latch Enable Logic Levels in Synchronous and Asynchronous Modes Operation Asynchronous Bus Read X Bus Write X or toggling Address Latch Toggling Standby X ...

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R FPGA Configuration Overview Platform Flash XL enables the rich set of Virtex-5 FPGA configuration features without additional glue logic. The device delivers the FPGA bitstream at power-on through a 16-bit data bus at data rates up to 800 Mb/s. ...

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R Slave-SelectMAP Configuration Mode Platform Flash XL achieves maximum configuration performance when the Virtex-5 FPGA is in Slave- SelectMAP configuration mode. In the Slave-SelectMAP mode, a stable, external clock source can drive the synchronous bitstream transfer from the device to ...

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R X-Ref Target - Figure 7 3.3V 1 VREF (1) TMS (1) TCK (1) TDO (1) TDI N/C N/C 14 Platform Flash XL 1.8V VDD 3.3V VPP VDDQ RP READY_WAIT (3) K 3.3V A[22: DQ[15:0] VSSQ ...

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R Alternate Configuration Modes Platform Flash XL is optimized for the Virtex-5 FPGA Slave- SelectMAP configuration mode. Alternatively, Platform Flash XL can configure a Virtex-5 FPGA via the Master- SelectMAP or Master-BPI-Up mode, albeit with compromises. Master-Select Mode Platform Flash ...

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R Programming Overview Programming solutions satisfying the requirements for each product phase are available for Platform Flash XL. ISE software provides integrated programming support for the FPGA design engineer in the prototyping environment. Third-party programming support is also available for ...

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R Bus Operations There are six standard bus operations that control the device: Bus Read, Bus Write, Address Latch, Output Disable, Standby and Reset (Table Bus Read Bus Read operations are used to output the contents of the Memory Array, ...

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R Command Interface All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. An internal Program/Erase Controller handles all timings and verifies the correct execution of the ...

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R into Read Electronic Signature mode. Subsequent Bus Read cycles output Electronic Signature data, and the Program/Erase controller continues to program or erase in the background. The Read Electronic Signature command only changes the read mode of the addressed bank. ...

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R After the command is issued, the addressed bank automatically enters the Status Register mode and further reads within the bank output the Status Register contents. The only operation permitted during Blank Check is Read Status Register. Dual Operations are ...

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R Buffer Enhanced Factory Program Command The Buffer Enhanced Factory Program command has been specially developed to speed up programming in manufacturing environments where the programming time is critical. The command is used to program one or more Write Buffer(s) ...

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R Program/Erase Suspend Command The Program/Erase Suspend command is used to pause a Program or Block Erase operation. The command can be addressed to any bank. The Program/Erase Resume command is required to restart the suspended operation. One Bus Write ...

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R Set Configuration Register Command The Set Configuration Register command is used to write a new value to the Configuration Register. Two Bus Write cycles are required to issue the Set Configuration Register command: • The first cycle sets up ...

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R (1) Table 7: Standard Commands Commands Read Array 1+ Read Status Register 1+ Read Electronic 1+ Signature Read CFI Query 1+ Clear Status Register 1 Block Erase 2 Program 2 (4) Buffer Program n+4 Program/Erase Suspend 1 Program/Erase Resume ...

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R Table 8: Factory Commands Command Phase Blank Check 2 Setup 2 Buffer Enhanced Program/ ≥32 Factory Program (3) Verify Exit 1 Notes Word Address in targeted bank, BKA = Bank Address, PD =Program Data ...

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R Table 10: Protection Register Locks Lock Number Address Bits bit 0 Lock 1 bit 1 80h bits bit 0 bit 1 bit 2 Lock 2 – 89h bit 13 bit 14 bit 15 X-Ref Target - ...

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R Status Register The Status Register provides information on the current or previous program or erase operations. A Read Status Register command is issued to read the contents of the Status Register, refer to "Read Status Register Command," page 14 ...

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R Program/Erase Controller Status Bit (SR7) The Program/Erase Controller Status bit indicates whether the Program/Erase Controller is active or inactive in any bank. When this bit is Low (set to ‘0’), the Program/Erase Controller is active; when the bit is ...

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R Block Protection Status Bit (SR1) The Block Protection Status bit is used to identify if a Program or Block Erase operation tried to modify the contents of a locked or locked-down block. When this bit is High (set to ...

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R Configuration Register The Configuration Register is used to configure the type of bus access that the memory performs. Refer to page 34 for details on read operations. The Configuration Register is set through the Command Interface using the Set ...

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R Read Mode Select Bit (CR15) The Read Select bit, CR15, is used to switch between Asynchronous and Synchronous Read operations. When this bit is set to ’1’, read operations are asynchronous; when set to ’0’, read operations are synchronous. ...

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R Wrap Burst Bit (CR3) The Wrap Burst bit (CR3) is used to select between wrap and no wrap. Synchronous burst reads can be confined inside the 16-word boundary (wrap) or overcome the boundary (no wrap). When ...

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R Table 14: Burst Type Definition Start Address 4 Words 0-1-2-3 0 1-2-3-0 1 2-3-0-1 2 3-0-1-2 3 7-4-5 0-1-2-3 0 1-2-3-4 1 2-3-4-5 2 3-4-5-6 3 7-8-9-10 7 12-13-14-15 12 13-14-15-WAIT-16 13 14-15-WAIT-WAIT-16-17 14 ...

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R X-Ref Target - Figure A22–A0 VALID ADDRESS DQ15–DQ0 Wait CR8 = ‘0’ CR10 = ‘0’ Wait CR8 = ‘1’ CR10 = ‘0’ Wait CR8 = ‘0’ CR10 = ‘1’ Wait CR8 = ‘1’ CR10 = ...

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R X-Ref Target - Figure 12 First Address Latching Sequence DDQ T VHRWZ READY_WAIT T RWRT RWHKL K Address not Valid A0–A22 DQ0–DQ15 Notes tied High. 2. Address is latched on ...

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R X-Ref Target - Figure 14 T RWLRWH READY_WAIT G High A0-A22 DQ0-DQ15 Dk Dn DATA VALID Notes and Dn indicate the Data valid after k and n clock cycles, respectively. 2. This figure applies ...

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R X-Ref Target - Figure PLRWH T RWL READY_WAIT T PLRWL G High A0−A22 Address not Valid DQ0−DQ15 X-Ref Target - Figure 17 T RPLRPH RP T RPHRWZ READY_WAIT T RPLRWL Low G High ...

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R Read Modes Read operations can be performed in two different ways depending on the settings in the Configuration Register. If the clock signal is ‘don’t care’ for the data output, the read operation is asynchronous; if the data output ...

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R A Synchronous Burst Read operation is suspended when Chip Enable (E) is Low and the current address is latched (on a Latch Enable rising edge valid clock edge). The Clock signal is then halted at V ...

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R Dual Operations and Multiple Bank Architecture The Multiple Bank Architecture of Platform Flash XL gives greater flexibility for software developers to split the code and data spaces within the memory array. The Dual Operations feature simplifies the software management ...

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R Table 17: Dual Operation Limitations Current Status Programming / Erasing Parameter Blocks Located in Parameter Bank Programming / Erasing Main Blocks Not Located in Parameter Bank Programming OTP DS617 (v2.1) May 14, 2008 Preliminary Product Specification Platform Flash XL ...

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R Block Locking Platform Flash XL features an instant, individual block-locking scheme, allowing any block to be locked or unlocked with no latency. This locking scheme has three levels of protection: • Lock/Unlock – this first level allows software only ...

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R Table 18: Lock Status (1) Current Protection Status Program/Erase Current State Allowed 1,0,0 (2) 1,0,1 – 1,1,0 1,1,1 – 0,0,0 (2) 0,0,1 – 0,1,1 – Notes: 1. The lock status is defined by the write protect pin and by ...

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R Power-On Reset To ensure a correct power-up sequence of Platform Flash XL, the V ramp time must not be shorter than DD VDDPOR 200 μs or longer than 50 ms during power-up (see Figure 19, page 41). ...

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R X-Ref Target - Figure DDPOR V DDPD Notes slow-ramping V power supply can still be below the minimum operating voltage when the READY_WAIT pin is released. In this case, the DD configuration ...

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R First Address Latching Sequence The first address latching sequence (FALS) is one of the key features of Platform Flash XL. This particular sequence, shown in Figure 20, page 42 and Figure 22, page allows the device to latch the ...

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R X-Ref Target - Figure DDQ READY_WAIT G High RP E Low L K A0–A22 DQ0–DQ15 Figure 21: First Address Latching Sequence (FALS) Clock is not Free Running and G Transitions High-to-Low after READY_WAIT Goes High ...

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R X-Ref Target - Figure DDQ READY_WAIT T GLRWH G High RP E Low AVRWH A0–A22 DQ0–DQ15 Figure 22: First Address Latching Sequence (FALS): Clock is Free Running Table 20: FALS Sequence Timings ...

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R Program and Erase Times and Endurance Cycles Table 21 lists both program and erase times plus the number of program/erase cycles per block. Exact erase times can vary depending on the memory array condition. The best case is when ...

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R Maximum Rating Stressing the device above the rating listed in ratings only, and proper operation of the device at these or any other conditions above those indicated in this specification is not implied. Exposure to Absolute Maximum Rating conditions ...

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R X-Ref Target - Figure 24 0.1 µF Notes includes JIG capacitance. L X-Ref Target - Figure 25 0.1 µF Notes includes JIG capacitance. L Figure 25: Connecting the READY_WAIT Pin when Using the Device DS617 ...

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R (1) Table 24: Capacitance Symbol Parameter C Input capacitance IN C Output capacitance OUT Notes: 1. Sampled only, not 100% tested. Table 25: DC Characteristics: Currents Symbol Parameter I Input leakage current LI I Output leakage current LO Supply ...

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R Table 26: DC Characteristics: Voltages Symbol Parameter V Input Low voltage IL V Input High voltage IH V Output Low voltage OL V Output High voltage program voltage-logic PP1 program voltage factory PPH ...

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R X-Ref Target - Figure 27 A3–A22 T AVAV A0–A2 VALID ADDRESS T AVLH L T LLLH T LLQV T ELLH E T ELQV T ELQX G T GLTV T ELTV Hi-Z (1) READY_WAIT T GLQV T GLQX DQ0–DQ15 Valid ...

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R Table 27: Asynchronous Read AC Characteristics Symbol Alt T AVAV T AVQV T AVQV1 (1) T AXQX T ELTV (2) T ELQV (1) T ELQX T EHTZ (1) T EHQX (1) T EHQZ (2) T GLQV (1) T GLQX ...

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R X-Ref Target - Figure 28 Hi-Z DQ0–DQ15 A0–A22 VALID ADDRESS T AVLH T LLLH L T LLKH T AVKH ( ELKH KHAX E G High W T ELTV Hi-Z READY_WAIT Address Latch Notes: 1. The number ...

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R Table 28: Synchronous Read AC Characteristics Symbol T T AVKH T T ELKH (3) T ELTV T EHEL (3) T EHTZ T T KHAX T KHQV T (3) T KHTV T KHQX T (3) T KHTX T T LLKH ...

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R X-Ref Target - Figure 29 A0–A22 L ( ELKH E G High W Hi-Z DQ0–DQ15 Hi-Z (1,2) READY_WAIT Notes: 1. The READY_WAIT signal is configured to be active during wait state. READY_WAIT signal is active Low. 2. ...

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R X-Ref Target - Figure 30 Hi-Z DQ0–DQ15 A0–A22 VALID ADDRESS T AVLH T LLLH L T LLKH T AVKH ( ELKH KHAX ELTV Hi-Z (2,5) READY_WAIT High W Notes: 1. The number of ...

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R X-Ref Target - Figure 32 A0–A22 BANK ADDRESS T T AVLH LHAX T LLLH L T ELLH E T ELWL G T GHWL W T DVWH COMMAND DQ0–DQ15 SET-UP COMMAND Figure 32: Write AC Waveforms, ...

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R Table 29: Write AC Characteristics, Write Enable Controlled Symbol Alt T T Address Valid to Next Address Valid AVAV WC T Address Valid to Latch Enable High AVLH (2) T Address Valid to Write Enable High AVWH T T ...

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R X-Ref Target - Figure 33 BANK ADDRESS A0–A22 T T AVLH LHAX T LLLH L T ELLH W T WLEL G T GHEL E T ELEH T DVEH DQ0–DQ15 COMMAND SET-UP COMMAND Figure 33: Write ...

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R Table 30: Write AC Characteristics, Chip Enable Controlled Symbol Alt T T Address Valid to Next Address Valid AVAV WC T Address Valid to Chip Enable High AVEH T Address Valid to Latch Enable High AVLH T T Data ...

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R Table 31: Reset and Power-Up AC Characteristics Symbol Reset Low to: T RPLWL Write Enable Low, T RPLEL Chip Enable Low, T RPLGL Output Enable Low, T RPLLL Latch Enable Low Reset High to: T RPHWL Write Enable Low ...

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R Table 32: Power-Up Timing Characteristics Symbol (1) T READY_WAIT Low driven from the device RWL T READY_WAIT pulse driven from the system RWLRWH (2) T READY_WAIT rise time RWRT T Time required to release the READY_WAIT pin after RP ...

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R Package Mechanical X-Ref Target - Figure BALL A1 A Figure 36: 10 × 13 mm, 8 × 8 Active Ball Array, 1 mm-Pitch FT64, Bottom View Package Outline Table 33: Package Mechanical Data for ...

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R Ordering Information X-Ref Target - Figure 37 Example: XCF128X FTG64 C Device Type Package Type FT64 = 64-ball, Fine-Pitch Thin Ball Grid Array FTG64 = 64-ball, Fine-Pitch Thin Ball Grid Array, Pb-free Valid Ordering Combinations Table 34: Valid Ordering ...

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R Appendix A: Block Address Tables Table 35: Boot Block Addresses (1) Bank Parameter Bank Bank 1 Bank 2 Bank 3 DS617 (v2.1) May 14, 2008 Preliminary Product Specification Platform Flash XL High-Density Storage and Configuration Device # Size (Kword) ...

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R Table 35: Boot Block Addresses (Cont’d) (1) Bank Bank 4 Bank 5 Bank 6 Bank 7 Bank 8 DS617 (v2.1) May 14, 2008 Preliminary Product Specification Platform Flash XL High-Density Storage and Configuration Device # Size (Kword ...

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R Table 35: Boot Block Addresses (Cont’d) (1) Bank Bank 9 Bank 10 Bank 11 Bank 12 Bank 13 DS617 (v2.1) May 14, 2008 Preliminary Product Specification Platform Flash XL High-Density Storage and Configuration Device # Size (Kword ...

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R Table 35: Boot Block Addresses (Cont’d) (1) Bank Bank 14 Bank 15 Notes: 1. There are two Bank Regions: Bank Region 1 contains all the banks made up of main blocks only; Bank Region 2 contains the banks made ...

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R Appendix B: Common Flash Interface The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from flash memory devices. This interface allows system software to query the device to determine various electrical and timing ...

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R Table 38: CFI Query System Interface Information Offset Data V Logic Supply Minimum Program/Erase or Write voltage DD 01Bh 0017h bit BCD value in volts bit BCD value in 100 millivolts V Logic ...

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R Table 40: Primary Algorithm-Specific Extended Query Table Offset Data 0050h (P)h = 10Ah 0052h 0049h (P+3)h = 10Dh 0031h (P+4)h = 10Eh 0033h (P+5)h = 10Fh 00E6h 0003h (P+7)h = 111h 0000h (P+8)h = 112h 0000h (P+9)h = 113h ...

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R Table 41: Protection Register Information Offset Data (P+E)h = 118h 0002h (P+F)h = 119h 0080h (P+10)h = 11Ah 0000h (P+ 11)h = 11Bh 0003h (P+12)h = 11Ch 0003h (P+13)h = 11Dh 0089h (P+14)h = 11Eh 0000h (P+15)h = 11Fh ...

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R Table 44: Bank and Erase Block Region 1 Information Offset Data (P+24)h = 12Eh 0Fh (P+25)h = 12Fh 00h (P+26)h = 130h 11h (P+27)h = 131h 00h (P+28)h = 132h 00h (P+29)h = 133h 01h (P+2A)h = 134h 07h ...

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R Table 45: Bank and Erase Block Region 2 Information Offset Data (P+32)h = 13Ch 01h (P+33)h = 13Dh 00h (P+34)h = 13Eh 11h (P+35)h = 13Fh 00h (P+36)h = 140h 00h (P+37)h = 141h 02h (P+38)h = 142h 06h ...

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R Appendix C: Flowcharts and Pseudocodes X-Ref Target - Figure 39 Start (3) Write 40h or 10h Write Address & Data Read Status (3) Register NO SR7 = 1 YES Invalid SR3 = 0 Error YES NO ...

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R X-Ref Target - Figure 40 Start Write Block Address & BCh Write Block Address & CBh Read (1) Status Register NO SR7 = 1 YES YES Command Sequence SR4 = 1 SR5 = 1 NO Blank Check Error SR5 ...

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R X-Ref Target - Figure 41 Start Buffer Program E8h Command, Start Address Read Status Register NO SR7 = 1 YES (1) Write n , Start Address Write Buffer Data, Start Address YES ...

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R X-Ref Target - Figure 42 Start Write B0h Write 70h Read Status Register NO SR7 = 1 YES NO Program Complete SR2 = 1 Write FFh Read Data YES Write FFh Read data from another address Write D0h (1) ...

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R X-Ref Target - Figure 43 Start (2) Write 20h Write Block Address & D0h Read Status (2) Register NO SR7 = 1 YES Invalid SR3 = 0 Error YES YES Command SR4, SR5 = 1 Sequence ...

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R X-Ref Target - Figure 44 Start Write B0h Write 70h Read Status Register NO SR7 = 1 YES NO SR6 = 1 YES Write FFh Read data from another block, Program, Set Configuration Register or Block Protect/Unprotect/Lock Write D0h ...

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R X-Ref Target - Figure 45 Start (1) Write 60h Write 01h, D0h or 2Fh (1) Write 90h Read Block Lock States NO Locking change confirmed? YES (1) Write FFh End Notes: 1. Any address within the bank can equally ...

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R X-Ref Target - Figure 46 Start (3) Write C0h Write Address & Data Read Status (3) Register NO SR7 = 1 YES Invalid SR3 = 0 Error YES NO Program SR4 = 0 Error YES NO ...

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R Start Write 80h to Address WA1 Write D0h to Address WA1 Read Status Register NO SR7 = 0 NO SR4 = 1 Initialize count Write PDX Read Status Register Address WA1 SR3 and SR1for errors Increment ...

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R Appendix D: Command Interface State Tables Table 46: Command Interface States – Modify Table, Next State Current CI State Program Ready Ready Setup Lock/CR Setup Setup OTP IS in OTP Busy OTP Busy Busy IS in OTP busy Setup ...

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R Table 46: Command Interface States – Modify Table, Next State Current CI State Setup Ready (error Erase Busy Erase Busy Busy IS in Erase Erase Busy Erase Program Suspend Suspend ...

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R Table 46: Command Interface States – Modify Table, Next State Current CI State Buffer Suspend Suspend Suspend Program Erase Suspend (Cont’ Suspend in ES Setup Blank Check ...

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R Table 47: Command Interface States – Modify Table, Next Output State Current CI State Program Setup Erase Setup OTP Setup Program Setup in Erase Suspend BEFP Setup BEFP Busy Buffer Program Setup Buffer Program Load 1 Buffer Program Load ...

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R Table 47: Command Interface States – Modify Table, Next Output State Current CI State OTP Busy Ready Program Busy Erase Busy Buffer Program Busy Program/Erase Suspend Buffer Program Suspend Array Program Busy in Erase Suspend Buffer Program Busy in ...

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R Table 48: Command Interface States – Lock Table, Next State Current CI State Lock/CR Setup( (2) Setup (60h) Ready Lock/CR Setup Lock/CR Setup Ready (Lock error) Setup OTP Busy IS in OTP busy Setup Busy IS in Program Program ...

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R Table 48: Command Interface States – Lock Table, Next State Current CI State Lock/CR Setup( (2) Setup (60h) Setup Buffer Load 1 Buffer Program Confirm in Erase Suspend when count =0; Else Buffer Program Buffer Load 2 Confirm Buffer ...

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R Table 49: Command Interface States – Lock Table, Next Output State Blank Current CI Lock/CR Check State (3) Setup ( setup 60h) (BCh) Program Setup Erase Setup OTP Setup Program Setup in Erase Suspend BEFP Setup BEFP Busy Buffer ...

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R Table 49: Command Interface States – Lock Table, Next Output State Blank Current CI Lock/CR Check State (3) Setup ( setup 60h) (BCh) OTP Busy Ready Program Busy Erase Busy Buffer Program Busy Program/Eras e Suspend Buffer Program Suspend ...

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R Revision History The following table shows the revision history for this document. Date Version 12/13/07 1.0 Initial Xilinx release. 03/31/08 2.0 Added bus operations and advance device specifications: • Expanded • Added the following sections: ♦ ♦ ♦ ♦ ...