xc5vlx330 Xilinx Corp., xc5vlx330 Datasheet - Page 23

• Manufacturer Part Number: xc5vlx330
• Description: Platform Flash Xl High-density Storage And Configuration Device
• Manufacturer: Xilinx Corp.

Status Register
The Status Register provides information on the current or
previous program or erase operations. A Read Status
Register command is issued to read the contents of the
Status Register, refer to
page 14
Register is latched and updated on the falling edge of the
Chip Enable or Output Enable signals and can be read until
Chip Enable or Output Enable returns to V
The Status Register can only be read using single
asynchronous or synchronous reads. Bus Read operations
from any address within the bank always read the Status
Register during program and erase operations if no Read
Array command is issued.
Table 11: Status Register Bits
DS617 (v2.1) May 14, 2008
Preliminary Product Specification
Notes:
1.
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
Bit
Logic level '1' is High, '0' is Low.
for more details. To output the contents, the Status
Status (Buffer Enhanced
Factory Program mode)
Block Protection Status
R
Multiple Word Program
Erase Suspend Status
Erase/Blank Check
Program Suspend
Bank Write Status
Program Status
P/E.C. Status
V
PP
Name
Status
Status
Status
"Read Status Register Command,"
Status
Status
Status
Status
Status
Type
Error
Error
Error
Error
IH
.
Level
Logic
Platform Flash XL High-Density Storage and Configuration Device
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
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(1)
Ready
Busy
Erase suspended
Erase In progress or completed
Erase/blank check error
Erase/blank check success
Program error
Program success
V
V
Program suspended
Program In progress or completed
Program/erase on protected block, abort
No operation to protected block
PP
PP
The various bits convey information about the status and
any errors of the operation. Bits SR7, SR6, SR2 and SR0
give information on the status of the device and are set and
reset by the device. Bits SR5, SR4, SR3 and SR1 give
information on errors and are set by the device but must be
reset by issuing a Clear Status Register command or a
hardware reset.
If an error bit is set to ‘1’, the Status Register should be
reset before issuing another command.
The bits in the Status Register are summarized in
invalid, abort
OK
SR7 = ‘1’
SR7 = ‘0’
SR7 = ‘1’
SR7 = ‘0’
SR7 = ‘1’
SR7 = ‘0’
SR7 = ‘1’
SR7 = ‘0’
Not allowed
Program or erase operation in a bank other
than the addressed bank
No program or erase operation in the device
Program or erase operation in addressed
bank
Not allowed
The device is NOT ready for the next Buffer
loading or is going to exit the BEFP mode
The device has exited the BEFP mode
The device is ready for the next Buffer
loading
Definition
Table
11.
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