xc5vlx330 Xilinx Corp., xc5vlx330 Datasheet - Page 9

• Manufacturer Part Number: xc5vlx330
• Description: Platform Flash Xl High-density Storage And Configuration Device
• Manufacturer: Xilinx Corp.

Slave-SelectMAP Configuration Mode
Platform Flash XL achieves maximum configuration
performance when the Virtex-5 FPGA is in Slave-
SelectMAP configuration mode. In the Slave-SelectMAP
mode, a stable, external clock source can drive the
synchronous bitstream transfer from the device to the
Virtex-5 FPGA up to the maximum burst read frequency
(T
in the Virtex-5 FPGA Configuration User Guide for details of
the Slave-SelectMAP mode.
In the Slave-SelectMAP configuration mode, the
configuration sequence is as follows:
1. A system event such as power-up initiates the FPGA
2. The FPGA and Platform Flash XL release their
3. The FPGA samples its mode pins to determine the
DS617 (v2.1) May 14, 2008
Preliminary Product Specification
CLK
configuration process. External passive components
default the device for output read operation.
respective INIT_B and READY_WAIT pins,
synchronizing the start of the configuration process.
Slave-SelectMAP configuration mode.
). See the SelectMAP Configuration Interface section
R
Platform Flash XL High-Density Storage and Configuration Device
www.xilinx.com
4. The device latches its starting address from the default,
5. Each 16-bit word of the bitstream is synchronously
6. The FPGA begins operation and asserts DONE to
The Virtex-5 family’s Slave-SelectMAP configuration mode
includes the following significant features and requirements:
•
•
•
Figure 7, page 10
Virtex-5 FPGA connected to a Platform Flash XL for Slave-
SelectMAP configuration mode.
static state of the address bus for its impending burst
read operation.
transferred from the device to the FPGA at each rising
edge of the configuration clock. An external clock
source is required to drive the configuration clock.
indicate the completion of the configuration procedure.
A external clock source drives the synchronous
bitstream transfer resulting in a precise FPGA
configuration time.
On-board pull-up or pull-down resistors set the device
control pins for output read mode.
On-board pull-up or pull-down resistors set the device
burst read start address.
shows an example connection of a
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