ep2a40b724i8 Altera Corporation, ep2a40b724i8 Datasheet - Page 8

• Manufacturer Part Number: ep2a40b724i8
• Description: Programmable Logic Device Family
• Manufacturer: Altera Corporation

APEX II Programmable Logic Device Family Data Sheet
Figure 1. APEX II Device Block Diagram
8
Four-input LUT
for data path and
DSP functions.
Product-term
integration for
high-speed
control logic and
state machines.
Clock Management Circuitry
ClockLock
IOE
IOE
Product Term
Product Term
Memory
Memory
Table 4
APEX II devices provide eight dedicated clock input pins and four
dedicated fast I/O pins that globally drive register control inputs,
including clocks. These signals ensure efficient distribution of high-speed,
low-skew control signals. The control signals use dedicated routing
channels to provide short delays and low skew. The dedicated fast signals
can also be driven by internal logic, providing an ideal solution for a clock
divider or internally-generated asynchronous control signal with high
fan-out. The dedicated clock and fast I/O pins on APEX II devices can also
feed logic. Dedicated clocks can also be used with the APEX II general-
purpose PLLs for clock management.
Table 4. APEX II Device Resources
LUT
IOE
LUT
IOE
EP2A15
EP2A25
EP2A40
EP2A70
Device
lists the resources available in APEX II devices.
Product Term
Product Term
Memory
Memory
LUT
IOE
LUT
IOE
MegaLAB Rows
Product Term
Product Term
Memory
Memory
LUT
LUT
IOE
IOE
26
38
40
70
Product Term
Product Term
Memory
Memory
LUT
LUT
IOE
IOE
MegaLAB
Columns
4
4
4
4
FastTrack
Interconnect
IOE
IOE
LUT
Altera Corporation
Flexible integration
of embedded
memory, including
CAM, RAM,
ROM, FIFO, and
other memory
functions.
IOEs support
PCI, GTL+,
SSTL-3, LVDS,
and other
standards.
ESBs
104
152
160
280