mc68hc908mr24 Freescale Semiconductor, Inc, mc68hc908mr24 Datasheet - Page 163

• Manufacturer Part Number: mc68hc908mr24
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

9.7 Fault Protection
MC68HC908MR24 — Rev. 4.1
Freescale Semiconductor
Address:
Conditions may arise in the external drive circuitry which require that the
PWM signals become inactive immediately, such as an overcurrent fault
condition. Furthermore, it may be desirable to selectively disable
PWM(s) solely with software.
One or more PWM pins can be disabled (forced to their inactive state)
by applying a logic high to any of the four external fault pins or by writing
a logic high to either of the disable bits (DISX and DISY in PWM control
register 1).
scheme. While the PWM pins are disabled, they are forced to their
inactive state. The PWM generator continues to run — only the output
pins are disabled.
To allow for different motor configurations and the controlling of more
than one motor, the PWM disabling function is organized as two banks,
bank X and bank Y. Bank information combines with information from
the disable mapping register to allow selective PWM disabling. Fault
pin 1, fault pin 2, and PWM disable bit X constitute the disabling function
of bank X. Fault pin 3, fault pin 4, and PWM disable bit Y constitute the
disabling function of bank Y.
disable mapping write-once register and the decoding scheme of the
bank which selectively disables PWM(s). When all bits of the disable
mapping register are set, any disable condition will disable all PWMs.
A fault can also generate a CPU interrupt. Each fault pin has its own
interrupt vector.
Reset:
Read:
Write:
Pulse-Width Modulator for Motor Control (PWMMC)
$0037
Bit 7
Bit 7
1
Figure 9-25
Figure 9-24. PWM Disable Mapping
Bit 6
6
1
Write-Once Register (DISMAP)
shows the structure of the PWM disabling
Bit 5
5
1
Pulse-Width Modulator for Motor Control (PWMMC)
Figure 9-24
Bit 4
4
1
Bit 3
and
3
1
Figure 9-26
Bit 2
2
1
Advance Information
Bit 1
1
1
show the
Bit 0
Bit 0
1
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