mc68hc908mr24 Freescale Semiconductor, Inc, mc68hc908mr24 Datasheet - Page 178

• Manufacturer Part Number: mc68hc908mr24
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Pulse-Width Modulator for Motor Control
9.10.5 PWM Control Register 2
Advance Information
178
NOTE:
NOTE:
The user should initialize the PWM registers and set the LDOK bit before
enabling the PWM.
A PWM CPU interrupt request can still be generated when LDOK is 0.
PWMEN — PWM Module Enable Bit
PWM control register 2 (PCTL2) controls the PWM load frequency, the
PWM correction method, and the PWM counter prescaler. For ease of
software and to avoid erroneous PWM periods, some of these register
bits are buffered. The PWM generator will not use the prescaler value
until the LDOK bit has been set, and a new PWM cycle is starting. The
correction bits are used at the beginning of each PWM cycle (if the
ISENSx bits are configured for software correction). The load frequency
bits are not used until the current load cycle is complete.
The user should initialize this register before enabling the PWM.
Pulse-Width Modulator for Motor Control (PWMMC)
automatically cleared after the new values are loaded or can be
manually cleared before a reaload by writing a 0 to it. Reset clears
LDOK.
This read/write bit enables and disables the PWM generator and the
PWM pins. When PWMEN is clear, the PWM generator is disabled
and the PWM pins are in the high-impedance state (unless
OUTCTL = 1).
When the PWMEN bit is set, the PWM generator and PWM pins are
activated.
For more information, see
1 = Load prescaler, modulus, and PWM values.
0 = Do not load new modulus, prescaler, and PWM values.
1 = PWM generator and PWM pins enabled
0 = PWM generator and PWM pins disabled
9.8 Initialization and the PWMEN
MC68HC908MR24
Freescale Semiconductor
—
Rev. 4.1
Bit.