mc68hc908mr24 Freescale Semiconductor, Inc, mc68hc908mr24 Datasheet - Page 243

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mc68hc908mr24

Manufacturer Part Number
mc68hc908mr24
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
12.7 I/O Signals
12.7.1 TIMB Clock Pin (PTD4/ATD12)
12.7.2 TIMB Channel I/O Pins (PTE1/TCH0B–PTE2/TCH1B)
MC68HC908MR24 — Rev. 4.1
Freescale Semiconductor
Port E shares three of its pins with the TIMB:
PTD4/ATD12 is an external clock input that can be the clock source for
the TIMB counter instead of the prescaled internal bus clock. Select the
PTD4/ATD12 input by writing logic 1s to the three prescaler select bits,
PS[2:0]. See
TCLK pulse width, TCLK
The maximum TCLK frequency is the least: 4 MHz or bus frequency 2.
PTD4/ATD12 is available as a general-purpose I/O pin or ADC channel
when not used as the TIMB clock input. When the PTD4/ATD12 pin is
the TIMB clock input, it is an input regardless of the state of the DDRE0
bit in data direction register E.
Each channel I/O pin is programmable independently as an input
capture pin or an output compare pin. PTE1/TCH0B and
PTE2/TCH1B
buffered PWM pins.
PTD4/ATD12 is an external clock input to the TIMB prescaler.
The two TIMB channel I/O pins are PTE1/TCH0B and
PTE2/TCH1B.
12.8.1 TIMB Status and Control
Timer Interface B (TIMB)
can be configured as buffered output compare or
LMIN
------------------------------------ -
bus frequency
or TCLK
1
HMIN
+
t
, is:
SU
Register. The minimum
Timer Interface B (TIMB)
Advance Information
243

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