mc68hc912dg128 Freescale Semiconductor, Inc, mc68hc912dg128 Datasheet - Page 172
mc68hc912dg128
Manufacturer Part Number
mc68hc912dg128
Description
M68hc12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC68HC912DG128.pdf
(452 pages)
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Clock Functions
11.6.13 Summary of STOP and pseudo-STOP Mode Exit Conditions
Technical Data
172
STOP exit without Limp Home
clock monitor disabled
Executing the STOP instruction
STOP exit in Limp Home mode
STOP exit in Limp Home mode
mode,
without Limp Home mode,
clock monitor enabled
with Delay
without Delay (Fast Stop
Recovery)
CAUTION:
Mode
Table 11-1. Summary of STOP Mode Exit Conditions
(NOLHM=1, CME=0, DLY=0)
If NOLHM is set to 1 and the CME and FCME bits are cleared, the limp
home clock is not used. In this mode, crystal activity is the only method
by which the device may recover from Pseudo-STOP. The device will
start execution with the EXTALi clock following 16 XCLK cycles.
Due to switching of the clock this configuration is not recommended.
Table 11-1
and pseudo-STOP modes using Interrupt, Key-interrupt and XIRQ.
A short RESET pulse should not be used to exit stop or pseudo-STOP
mode because Limp Home mode is automatically entered after RESET
(when V
oscillator startup time (as in power on reset) in order to remove the risk
of code runaway.
. .
Freescale Semiconductor, Inc.
For More Information On This Product,
NOLHM=1
CME=0
DLY=X
NOLHM=1
CME=1
DLY=X
NOLHM=0
CME=X
DLY=1
NOLHM=0
CME=X
DLY=0
Conditions
DDPLL
and
Go to: www.freescale.com
=V
Table 11-2
DD
Clock Functions
). The RESET wakeup pulse must be longer than the
Oscillator must be stable within 4096 XCLK cycles. XCLK
Use of DLY=0 only recommended with external clock.
When a STOP instruction is executed the MCU resets via
Oscillator must be stable within 4096
f
This mode is only recommended for use with an external
VCOMIN
can be modified by SLOW divider register.
the clock monitor reset vector.
the clock monitor circuit can be misled by EXTALi clock
into reporting a good signal before it has fully stabilised
clock source.
summarise the exit conditions from STOP
cycles or there is a possibility of code runaway as
Summary
MC68HC912DG128 — Rev 3.0
MOTOROLA
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