mc68hc912dg128 Freescale Semiconductor, Inc, mc68hc912dg128 Datasheet - Page 259
mc68hc912dg128
Manufacturer Part Number
mc68hc912dg128
Description
M68hc12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC68HC912DG128.pdf
(452 pages)
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MC68HC912DG128 — Rev 3.0
MOTOROLA
OR — Overrun Error Flag
NF — Noise Error Flag
FE — Framing Error Flag
PF — Parity Error Flag
Freescale Semiconductor, Inc.
New byte is ready to be transferred from the receive shift register to
the receive data register and the receive data register is already full
(RDRF bit is set). Data transfer is inhibited until this bit is cleared.
Set during the same cycle as the RDRF bit but not set in the case of
an overrun (OR).
Set when a zero is detected where a stop bit was expected. Clear the
FE flag by reading SCxSR1 with FE set and then reading SCxDR.
Indicates if received data’s parity matches parity bit. This feature is
active only when parity is enabled. The type of parity tested for is
determined by the PT (parity type) bit in SCxCR1.
For More Information On This Product,
0 = No overrun
1 = Overrun detected
0 = Unanimous decision
1 = Noise on a valid start bit, any of the data bits, or on the stop bit
0 = Stop bit detected
1 = Zero detected rather than a stop bit
0 = Parity correct
1 = Incorrect parity detected
Go to: www.freescale.com
Multiple Serial Interface
Serial Communication Interface (SCI)
Multiple Serial Interface
Technical Data
259
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