mpc823rg Freescale Semiconductor, Inc, mpc823rg Datasheet - Page 209
mpc823rg
Manufacturer Part Number
mpc823rg
Description
Mpc823 Powerquicc Integrated Communications Processor For Portable Systems
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MPC823RG.pdf
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Data Cache
Bits 3, 8, and 9—Reserved
These bits are reserved and must be set to 0.
CMD—Command
The following commands can be written to the CMD field to control and configure the data
cache. The machine must be in privilege mode (MSR
CCER1—Data Cache Error Type 1
This field is sticky and set by the hardware. It is read-only and cleared when read.
CCER2—Data Cache Error Type 2
This field is sticky and set by the hardware. It is read-only and cleared when read.
CCER3—Data Cache Error Type 3
This field is sticky and set by the hardware. It is read-only and cleared when read.
Bits 13–31—Reserved
These bits are reserved and must be set to 0.
0000 = Reserved.
0010 = Data Cache ENABLE .
0100 = Data Cache DISABLE .
0110 = LOCK LINE .
1000 = UNLOCK LINE .
1010 = UNLOCK ALL .
1100 = INVALIDATE ALL .
1110 = FLUSH Data Cache LINE .
0001 = SET FORCE WRITETHROUGH MODE .
0011 = CLEAR FORCE WRITETHROUGH MODE .
0101 = SET LITTLE-ENDIAN SWAP MODE .
0111 = CLEAR LITTLE-ENDIAN SWAP MODE .
Others = Reserved.
0 = No Error.
1 = Error.
0 = No Error.
1 = Error.
0 = No Error.
1 = Error.
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC823 REFERENCE MANUAL
Go to: www.freescale.com
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