mpc5644a Freescale Semiconductor, Inc, mpc5644a Datasheet - Page 8

• Manufacturer Part Number: mpc5644a
• Description: Mpc5644a Microcontroller Data Sheet
• Manufacturer: Freescale Semiconductor, Inc

Overview
1.2.5
The Memory Protection Unit (MPU) provides hardware access control for all memory references generated in a device. Using
preprogrammed region descriptors, which define memory spaces and their associated access rights, the MPU concurrently
monitors all system bus transactions and evaluates the appropriateness of each transfer. Memory references with sufficient
access control rights are allowed to complete; references that are not mapped to any region descriptor or have insufficient rights
are terminated with a protection error response.
The MPU has these major features:
1.2.6
The FMPLL allows the user to generate high speed system clocks from a 4 MHz to 40 MHz crystal oscillator or external clock
generator. Further, the FMPLL supports programmable frequency modulation of the system clock. The PLL multiplication
factor, output clock divider ratio are all software configurable. The PLL has the following major features:
1. EBI not available on all packages and is not available, as a master, for customer.
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Support for 16 memory region descriptors, each 128 bits in size
— Specification of start and end addresses provide granularity for region sizes from 32 bytes to 4 GB
— MPU is invalid at reset, thus no access restrictions are enforced
— Two types of access control definitions: processor core bus master supports the traditional {read, write, execute}
— Automatic hardware maintenance of the region descriptor valid bit removes issues associated with maintaining a
— Alternate memory view of the access control word for each descriptor provides an efficient mechanism to
— For overlapping region descriptors, priority is given to permission granting over access denying as this approach
Support for two XBAR slave port connections (SRAM and PBRIDGE)
— For each connected XBAR slave port (SRAM and PBRIDGE), MPU hardware monitors every port access using
— An access protection error is detected if a memory reference does not hit in any memory region or the reference
— 64-bit error registers, one for each XBAR slave port, capture the last faulting address, attributes, and detail
Input clock frequency from 4 MHz to 40 MHz
Reduced frequency divider (RFD) for reduced frequency operation without forcing the PLL to relock
3 modes of operation
— Bypass mode with PLL off
— Bypass mode with PLL running (default mode out of reset)
— PLL normal mode
Each of the three modes may be run with a crystal oscillator or an external clock reference
Programmable frequency modulation
— Modulation enabled/disabled through software
— Triangle wave modulation up to 100 kHz modulation frequency
— Programmable modulation depth (0% to 2% modulation depth)
— Programmable modulation frequency dependent on reference frequency
permissions with independent definitions for supervisor and user mode accesses; the remaining non-core bus
masters (eDMA, FlexRay, and EBI
coherent image of the descriptor
dynamically alter the access rights of a descriptor only
provides more flexibility to system software
the pre-programmed memory region descriptors
is flagged as illegal in all memory regions where it does hit. In the event of an access error, the XBAR reference
is terminated with an error response and the MPU inhibits the bus cycle being sent to the targeted slave device
information
Memory protection unit (MPU)
FMPLL
Preliminary—Subject to Change Without Notice
MPC5644A Microcontroller Data Sheet, Rev. 4
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) support {read, write} attributes
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