dp8344b National Semiconductor Corporation, dp8344b Datasheet - Page 145
dp8344b
Manufacturer Part Number
dp8344b
Description
Biphase Communications Processor?bcp
Manufacturer
National Semiconductor Corporation
Datasheet
1.DP8344B.pdf
(184 pages)
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Figure 6-3
6 0 Reference Section
LJMP Conditional Long Jump
Syntax
LJMP Rs p s nn
Affected Flags
None
Description
Conditionally transfers control to the instruction at the abso-
lute memory address nn if the bit in position p of register Rs
is equal to the state of the bit s The operand Rs may speci-
fy any active CPU register The value of p may be from 0 to
7 where 0 corresponds to the LSB of Rs and 7 corresponds
to the MSB of Rs The absolute value nn is 16 bits long
(range 0 to 64k) therefore all of instruction memory can be
addressed
Example
Long Jump to one of the receiver error handling routines
based on the contents of the Error Code Register ECR
Instruction Format
T-states
(2
Bus Timing
Operation
If Rs p
1
15
15
Determine error condition
EXX
OR
MOVE ECR R11
LJMP
LJMP
LJMP
LJMP
LJMP
then nn
a
0
2)
e
0
Opcode
x
0 1 3
01000000B TSR
R11 0 1 Software error
R11 1 1 Loss of Midbit
R11 2 1 Invalid Ending Seq
R11 3 1 Parity error
R11 4 1 Software error
s
0
PC
1
1
0
register absolute
s
8
nn
7
select main A alt B
set SEC in TSR
read ECR
and clear GIE
p
(Continued)
4
Rs
0
0
145
LJMP Unconditional Long Jump
Syntax
LJMP nn
LJMP
Affected Flags
None
Description
Unconditionally transfers control to the instruction at the
memory address specified by the operand The operand
may either specify an absolute instruction address nn (16
bits long) or an index register Ir which contains an instruc-
tion address Long Jump’s addressing range is from 0 to
64k (i e all of instruction memory can be addressed)
Example
Transfer control to the instruction labeled ‘‘Reset System’’
which may be located anywhere in instruction memory
Instruction Format
LJMP nn
LJMP
T-states
LJMP nn
LJMP
Bus Timing
LJMP nn
LJMP
Operation
LJMP nn
nn
LJMP
Ir
1
15
15
1
15
x
LJMP
x
1
1
PC
PC
0
0
Ir
Ir
Ir
Ir
Ir
0
0
Reset System
Opcode
1
1
1
1
Figure 6-3
Figure 6-1
absolute
indexed
(2
2
1
0
a
Opcode
0
1
2)
nn
0
0
go reset the system
0
6
v
00 IW
01 IX
10 IY
11 IZ
Ir
0
0
0
4
0
0
0
0
0
0
0
0
0
0
0
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