mc33389 Freescale Semiconductor, Inc, mc33389 Datasheet - Page 37
![no-image](/images/manufacturer_photos/0/2/263/freescale_semiconductor__inc_sml.jpg)
mc33389
Manufacturer Part Number
mc33389
Description
System Basis Chip With Low Speed Fault Tolerant Can
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC33389.pdf
(49 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
mc33389CDH
Manufacturer:
LATTICE
Quantity:
12
Part Number:
mc33389CDH
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
Company:
Part Number:
mc33389CDW
Manufacturer:
FREE
Quantity:
1 429
Company:
Part Number:
mc33389CDW
Manufacturer:
FREESCALE Semiconductor
Quantity:
38
Part Number:
mc33389CDW
Manufacturer:
MC
Quantity:
20 000
Company:
Part Number:
mc33389CDWR2
Manufacturer:
ON
Quantity:
10 736
Part Number:
mc33389DDWR2
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
mc33389DW
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
Table 27. GSLR Bit Definition
Table 28. Wake-Up Input Control Register (WUICR)
events during the Read operation.
Table 29. WUICR Bit Definition
Table 30. WUICR Bit Definition
Table 31. Wake-Up Input Status Register (WUISR)
Analog Integrated Circuit Device Data
Freescale Semiconductor
SHIFT
TXDOM
register and are set to 0 after a power-ON reset. A reset of WUICR1 and WUICR0 occurs when RST = Low.
Address
Address
WUICR
RESET
This register configures the wake-up level for the L0, L1, and L2 inputs. It reports the CAN wake-up and SPI (CS) wake-up
WUISR
RESET
This register reads back the wake input (L0, L1, L2) causing the SBC to wake-up.
The information is SPIWU and BUSWU is latched. Bits SPIWU and BUSWU will be reset by a read operation of the WUICR
$00C
$00F
0 = No failure on TX
1 = TX permanent dominant
1 = Ground shift above the threshold selected by GSLR1 and GSLR2
0 = No ground shift
The SHIFT information is latched until a read operation of the GSLR register occurs. The GSLR register is set to 0 after power-ON
reset. A reset of GSLR1 and GSLR0 occurs when RST = Low.
WUICR1
SPIWU
0
0
1
1
0
0
1
W
W
R
R
GSLR1
0
0
1
1
Bit 7
Bit 7
—
—
WUICR0
BUSWU
Bit 6
Bit 6
0
1
0
—
—
0
1
0
1
Bit 5
Bit 5
—
—
GSLR0
0
1
0
1
Bit 4
Bit 4
—
—
Positive and Negative Sensitive
SPIWU
Wake-Up Event on CAN Bus
Wake-Up Event on SPI Bus
Bit 3
Bit 3
Wake-Up Inputs Disabled
Negative Edge Sensitive
—
Positive Edge Sensitive
0
No Wake-Up Events
Description
Description
WUISR2
BUSWU
LOGIC COMMANDS AND REGISTERS
Bit 2
Bit 2
0
Typical Ground Shift Level
FUNCTIONAL DEVICE OPERATION
0
-1.2 V
-1.7 V
-2.2 V
WUISR1
0.7 V
WUCR1
Bit 1
Bit 1
0
0
WUISR0
WUICR0
Bit 0
Bit 0
0
0
33389
37