lan9420 Standard Microsystems Corp., lan9420 Datasheet - Page 109

• Manufacturer Part Number: lan9420
• Description: Lan9420/lan9420i Single-chip Ethernet Controller With Hp Auto-mdix Support And Pci Interface
• Manufacturer: Standard Microsystems Corp.

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
SMSC LAN9420/LAN9420i
4.3.6
31:23
22:20
19:17
BITS
16
RESERVED
Transmit Process State (TS)
This Read-Only field indicates the state of the transmit process. This field
does not generate an interrupt. The TS field is encoded as follows:
Receive Process State (RS)
This Read-Only field indicates the state of the receive process. This field
does not generate an interrupt. The RS field is encoded as follows:
Normal Interrupt Summary (NIS)
This bit is the logical OR of other bits within this register. Only unmasked
bits affect this register. Below is the list of bits:
DMAC_STATUS[0]: Transmit interrupt (TI)
DMAC_STATUS[2]: Transmit buffer unavailable (TU)
DMAC_STATUS[6]: Receive interrupt (RI)
DMAC_STATUS[14]: Early receive interrupt (ERI)
DMA Controller Status Register (DMAC_STATUS)
This register contains all of the status bits that the DMAC reports to the Host system. Most of the fields
in this register will cause an interrupt. Status can be checked as part of an interrupt service routine, or
by polling. DMAC interrupts can be masked in the DMAC_INTR_ENA register.
STATE
STATE
000
001
010
011
100
101
110
111
000
001
010
100
101
011
110
111
Offset:
Stopped - Reset or Stop command issued
Running - Fetching the transmit descriptor
Running - Waiting for the end of transmission
Running - Reading the data from memory and queuing into TX FIFO
RESERVED
RESERVED
Suspended - Transmit buffer underflow, or an unavailable transmit
descriptor
Running - Closing the transmit descriptor
Stopped - Reset or Stop receive command
Running - Fetching the receive descriptor
Running - Checking for end of receive packet before prefetch of next
descriptor
Running - Waiting for receive packet
Suspended - Unavailable receive descriptor
Running - Closing receive descriptor
Running - Flushing the current frame from the receive buffer because
of unavailable receive buffer
Running - Queuing the receive frame from the receive buffer into the
Host memory
DESCRIPTION
0014h
DESCRIPTION
DESCRIPTION
DATASHEET
109
Size:
32 bits
TYPE
R/WC
RO
RO
RO
Revision 1.1 (03-31-08)
DEFAULT
000b
000b
0b
-