lan9420 Standard Microsystems Corp., lan9420 Datasheet - Page 135

• Manufacturer Part Number: lan9420
• Description: Lan9420/lan9420i Single-chip Ethernet Controller With Hp Auto-mdix Support And Pci Interface
• Manufacturer: Standard Microsystems Corp.

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
SMSC LAN9420/LAN9420i
4.4.13Checksum Offload Engine Control Register (COE_CR)
31:17
BITS
15:2
16
1
0
RESERVED
TX Checksum Offload Engine Enable (TX_COE_EN)
The COE_EN may only be changed if the TX path is disabled. If it is desired
to disable the TX_COE_EN during run time, it is safe to do so only after the
MAC is disabled and the MIL is empty.
0: The TXCOE is bypassed
1: The TXCOE is enabled
RESERVED
RX Checksum Offload Engine Mode (RX_COE_MODE)
This register indicates whether the COE will check for VLAN tags or a
SNAP header prior to beginning its checksum calculation. In its default
mode, the calculation will always begin 14 bytes into the frame.
The COE_MODE may only be changed if the RX path is disabled. If it is
desired to change this value during run time, it is safe to do so only after
the MAC is disabled and the MIL is empty.
0: Begin checksum calculation after first 14 bytes of Ethernet Frame
1: Begin checksum calculation at start of L3 packet by adjusting for VLAN
tags and/or SNAP header.
RX Checksum Offload Engine Enable (RX_COE_EN)
The COE_EN may only be changed if the RX path is disabled. If it is
desired to disable the COE_EN during run time, it is safe to do so only after
the MAC is disabled and the MIL is empty.
0: The RXCOE is bypassed
1: The RXCOE is enabled
Note:
This register controls the RX and TX checksum offload engines
Offset:
When the RXCOE is enabled, automatic pad stripping must be
disabled (PADSTR bit of the
and vice versa. These functions cannot be enabled
simultaneously.
DESCRIPTION
00B0h
DATASHEET
MAC Control Register
135
Size:
(MAC_CR))
32 bits
.
TYPE
R/W
R/W
R/W
RO
RO
Revision 1.1 (03-31-08)
DEFAULT
0b
0b
0b
-
-