lan9420 Standard Microsystems Corp., lan9420 Datasheet - Page 51

• Manufacturer Part Number: lan9420
• Description: Lan9420/lan9420i Single-chip Ethernet Controller With Hp Auto-mdix Support And Pci Interface
• Manufacturer: Standard Microsystems Corp.

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
SMSC LAN9420/LAN9420i
3.4.6
3.4.7
3.4.7.1
3.4.7.2
5. The reception of a new frame will move the RX engine from the suspend state.
Note: Oversized RX packets must not cross from one buffer to another unless either the starting
Receive Descriptor Acquisition
The receive engine always attempts to acquire an extra descriptor in the anticipation of an incoming
frame. Descriptor acquisition is attempted if any of the following conditions are satisfied:
Suspend State Behavior
The following sections detail the suspend state behavior of the transmit and receive engines.
Transmit Engine
The Transmit Engine enters the suspended state when either of these conditions occurs:
In both of these cases the abnormal interrupt summary (AIS bit in the DMAC_STATUS register) and
the transmit interrupt (TI bit in the DMAC_STATUS register) are set and the appropriate status bit in
TDES0 is set. The position in the transmit list is retained. The retained position is that of the descriptor
following the descriptor that was last closed.
Note: The DMA controller does not automatically poll the transmit descriptor list. The driver must
Receive Engine
The Receive Engine enters the suspended state when a receive buffer is unavailable. If a frame arrives
when the receiver is in the suspended state, the receive engine re-fetches the descriptor and, if now
owned by the DMA controller, reenters the running state and starts frame reception. Receive polling
resumes from the last list position. The DMA controller generates a Receive Buffer Unavailable
interrupt (RU bit in the DMAC_STATUS register) only once - when entering the suspended state from
the running state. In the suspended state, if a new frame is received and a descriptor is still not
available, the frame is discarded. Only in the suspended state does the controller respond to a Receive
Poll Demand (for example, a buffer is available before the next incoming frame) and enter the running
state.
When the (SR) Start/Stop Receive bit (bit 1 of DMAC_CONTROL) sets immediately after being
placed in the running state
When the memory buffer ends before the frame ends for the current transfer
When the controller completes the reception of a frame and the current receive descriptor has been
closed
When the receive process is suspended because of a Host-owned buffer (RDES0[31]=0) and a
new frame is being received
When receive poll demand is issued
The DMA controller detects a descriptor owned by the Host system (TDES0[31]=0). To resume, the
driver must give the descriptor ownership to the DMA controller and then issue a poll demand
command.
A DMA transmission was aborted due to a local error.
to fetch the next descriptor and repeat the process unless it encounters a descriptor marked as
being owned by the Host system. If this occurs, the Receive Buffer Unavailable bit (RU) is set and
the receive engine enters the suspended state. If a new frame arrives while the receive engine is
in the suspended state, the DMA controller re-fetches the current descriptor. If the descriptor is now
owned by the DMAC, the receive process continues. If the descriptor is still owned by the Host
system, the frame is discarded and DMAC re-enters the suspend state. This process is repeated
for each received frame.
address of the 2nd buffer is DWORD aligned, or the oversized packet is to be discarded.
explicitly issue a transmit poll demand after rectifying the suspension cause.
DATASHEET
51
Revision 1.1 (03-31-08)